Journey Toward Process Convergence in TSV Technology

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001282-001321
Author(s):  
Sesh Ramaswami ◽  
John Dukovic
Keyword(s):  
Process Integration ◽  
Semiconductor Industry ◽  
Rapid Development ◽  
Chemical Mechanical Planarization ◽  
Cost Effective ◽  
Superior Performance ◽  
Wafer Level ◽  
Unit Process ◽  
Integration Schemes ◽  
Process Convergence

Continuous demand for more advanced electronic devices with higher functionality and superior performance in smaller packages is driving the semiconductor industry to develop new and more advanced 3D wafer-level interconnect technologies involving TSVs (through-silicon vias). The TSVs are created either on full-thickness wafer from the wafer front-side ¡V as part of wafer-fab processing during Middle-Of-Line (¡§via middle¡¨) or Back-End-Of-Line (¡§via last BEOL¡¨) ¡V or from the wafer backside after wafer thinning (¡§via last backside¡¨). Independent of the specific approach, the main steps include via etching, lining with insulator, copper barrier/seed deposition, via fill, and chemical mechanical planarization (CMP). Over the past year, the industry has been converging toward some primary unit processes and integration schemes for creating the TSVs. A common cost-of-ownership framework has also begun to emerge. Active collaboration underway among equipment suppliers, materials providers and end users is bringing about rapid development and validation of cost-effective TSV technology in end products. This presentation will address unit-process and integration challenges of TSV fabrication in the context of 20x100ƒÝm and 5x50ƒÝm baseline process flows at Applied Materials. Highlights of wafer-backside process integration involving wafers bonded to silicon or glass carriers will also be discussed.

Advances in Chemical-Mechanical Planarization

MRS Bulletin ◽  
2002 ◽  
Vol 27 (10) ◽  
pp. 743-751 ◽  
Author(s):  
Rajiv K. Singh ◽  
Rajeev Bajaj
Keyword(s):  
Surface Topography ◽  
Process Integration ◽  
Semiconductor Industry ◽  
Chemical Mechanical Planarization ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Fundamental Understanding ◽  
Copper Polishing ◽  
Future Growth

AbstractThe primary aim of this issue of MRS Bulletin is to present an overview of the materials issues in chemical–mechanical planarization (CMP), also known as chemical–mechanial polishing, a process that is used in the semiconductor industry to isolate and connect individual transistors on a chip. The CMP process has been the fastest-growing semiconductor operation in the last decade, and its future growth is being fueled by the introduction of copper-based interconnects in advanced microprocessors and other devices. Articles in this issue range from providing a fundamental understanding of the CMP process to the latest advancements in the field. Topics covered in these articles include an overview of CMP, fundamental principles of slurry design, understanding wafer–pad–slurry interactions, process integration issues, the formulation of abrasive-free slurries for copper polishing, understanding surface topography issues in shallow trench isolation, and emerging applications.

Cost Effective and High Performance 28nm FPGA with New Disruptive Silicon-Less Interconnect Technology (SLIT)

2014 ◽  
Vol 2014 (1) ◽  
pp. 000599-000605 ◽  
Author(s):  
Woon-Seong Kwon ◽  
Suresh Ramalingam ◽  
Xin Wu ◽  
Liam Madden ◽  
C. Y. Huang ◽  
...  
Keyword(s):  
High Performance ◽  
Process Integration ◽  
Cost Effective ◽  
Disruptive Innovation ◽  
Design Rule ◽  
Wind Condition ◽  
Silicon Etching ◽  
Wafer Level ◽  
Effective Manner ◽  
Interconnect Technology

This paper introduces the first comprehensive demonstration of new disruptive innovation technology comprising multiple Xilinx patent-pending innovations for highly cost effective and high performance Xilinx FPGA, which is so called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex® -7 2000T FPGA product. Chip-to-Wafer stacking, wafer level flux cleaning, micro-bump underfilling, mold encapsulation are newly developed. Of all technology elements, both full silicon etching with high etch selectivity to dielectric/fast etch rate and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. In order to manage the wafer warpage after full Si removal, a couple of knobs are identified and employed such as top reinforcement layer, micro-bump underfill properties tuning, die thickness/die-to-die space/total thickness adjustments. It's also discussed in the paper how the wafer warpage behaves and how the wafer warpge is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ~ −40 μm at room temperature for 25 mm × 31 mm in size and +20 μm ~ +25 μm at reflow temperature. Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T FCBGA package using TSV interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.

Reliability Study of Reference Semiconductor Encapsulation Materials for Biocompatible Packaging

2012 ◽  
Vol 2012 (1) ◽  
pp. 000148-000153
Author(s):  
Karl Malachowski ◽  
Karen Qian ◽  
Maaike Op de Beeck ◽  
Rita Verbeeck ◽  
George Bryce ◽  
...  
Keyword(s):  
Elevated Temperatures ◽  
Process Integration ◽  
Material Selection ◽  
Semiconductor Industry ◽  
Electrical Performance ◽  
Integration Scheme ◽  
Back Side ◽  
Wafer Level ◽  
Nitride Layers

Material selection is the key issue when developing a biocompatible packaging process for implantable electronic systems. To secure a reliable performance of the chip in such a package, its encapsulation has to be considered up-front in the wafer-level integration scheme. A differentiation of two main material types can be made:1) Insulating or passive materials functioning as a bi-directional diffusion barrier preventing body fluids leaking into the package causing systems malfunction due to possible materials corrosion and also avoiding a leakage of built-in materials to the in-vivo environment and2) Conductive or active materials as diffusion barriers, e.g. against copper diffusion or as direct external contacts responsible for electrical performance of the system. This study investigates the properties of two widely used insulating materials in the semiconductor industry, the nitride and the oxide. Both material types are deposited in a PECVD system using different temperatures; 400 ° C for CMOS compatibility and 200 ° C for wafer back side process integration when a temporary carrier system is used. The biocompatibility investigations of these materials (evaluated using cell lines and primary cells) show promising results. However, for the long term application, the stability results for the oxide layers show hydration effects resulting in material degradation where the nitride layers clearly show corrosion and are even etched when elevated temperatures are applied. This fact is surprising since nitride layers are widely used as a humidity barrier for various chip types but obviously not suitable for a direct contact with liquids. Various analysis methods using e.g. Fourier Transformed IR Spectroscopy or mass measurements substantiate this thesis.

New Stacked Die Interconnect Technology for High-Performance and Low-Cost FPGA

2015 ◽  
Vol 12 (3) ◽  
pp. 111-117
Author(s):  
Woon-Seong Kwon ◽  
Suresh Ramalingam ◽  
Xin Wu ◽  
Liam Madden ◽  
C. Y. Huang ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Integration ◽  
Cost Effective ◽  
Design Rule ◽  
Innovative Technology ◽  
Wind Condition ◽  
Wafer Level ◽  
Effective Manner ◽  
Interconnect Technology

This article introduces the first comprehensive demonstration of new innovative technology comprising multiple key technologies for highly cost-effective and high-performance Xilinx field programmable gate array (FPGA), which is so-called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex®-7 2000T FPGA product with chip-to-wafer stacking, wafer-level flux cleaning, microbump underfilling, mold encapsulation, and backside silicon removal. Of all technology elements, both full silicon removal process with faster etching and no dielectric layer damage and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. To manage the wafer warpage after full Si removal, a couple of knobs are identified and used such as top reinforcement layer, microbump underfill properties tuning, die thickness, die-to-die space, and total thickness adjustments. It is also discussed in the article how the wafer warpage behaves and how the wafer warpage is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ∼ −40 μm at room temperature (25°C) for 25 mm × 31 mm in size and +20 μm ∼ +25 μm at reflow temperature (250°C). Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T flip-chip ball grid array (FC-BGA) package using through silicon via interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.

Wafer-Level, Compliant, Off-Chip Interconnects for Next-Generation Low-K Dielectric/Cu IC’s

2006 ◽  
Author(s):  
Karan Kacker ◽  
George Lo ◽  
Suresh K. Sitaraman
Keyword(s):  
Dielectric Material ◽  
Semiconductor Industry ◽  
Cost Effective ◽  
Organic Substrate ◽  
Integrative Approach ◽  
Wafer Level ◽  
Technology Roadmap ◽  
Cte Mismatch ◽  
Compliant Interconnect ◽  
Low K

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors (ITRS) that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 70 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the CTE mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnect are less likely to crack or delaminate the low-K dielectric material in current and future ICs. The interconnects are also potentially cost effective as they can be fabricated using conventional wafer fabrication infrastructure. In this paper we present an integrative approach which uses interconnects with varying compliance and thus varying electrical preformance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermo-mechanical reliability concerns. We also discuss the reliability assessment results of helix interconnects assembled on an organic substrate. Results from mechanical characterization experiments are also presented.

Optimization of laser release layer, glass carrier, and organic build-up layer to enable RDL-first fan-out wafer-level packaging

2016 ◽  
Vol 2016 (1) ◽  
pp. 000190-000195 ◽  
Author(s):  
Alvin Lee ◽  
Jay Su ◽  
Baron Huang ◽  
Ram Trichur ◽  
Dongshun Bai ◽  
...  
Keyword(s):  
High Speed ◽  
Process Integration ◽  
Cost Effective ◽  
Wafer Level ◽  
Molding Compound ◽  
Fine Line ◽  
Glass Substrates ◽  
Laser Ablation Process ◽  
Wafer Level Packaging ◽  
Increasing Demand

Abstract With increasing demand for mobile devices to be lighter and thinner and consume less power while operating at high speed and high bandwidth, many equipment suppliers and assembly participants have invested great efforts to achieve fine-line fan-out wafer-level packaging (FOWLP). However, the inherent warp of reconstituted wafers, which can contribute to poor die placement accuracy and/or delamination at the interface of the build-up layer and carrier, remains a major challenge. In this study, the interactions among laser release layer, glass carrier, and build-up layer were evaluated for optimization of redistribution layer (RDL)–first FOWLP as a foundation to move toward fine-line FOWLP. In this study, a series of experiments incorporating glass carrier, laser release layer, and build-up layers were carried out to determine the optimal setup for RDL-first FOWLP. First, glass carriers (300 mm × 300 mm × 0.7 mm) with coefficients of thermal expansion of 3 and 8 ppm/°C were treated with 150-nm laser release layers. After deposition of 0.1 μm of sacrificial material on the glass carrier, 8-μm build-up layers were coated and patterned by lithography to electroplate Cu interconnections with a density of approximately 10% of the surface area. Subsequent to die attachment, molding compound was applied on top to form a 200-μm protective overcoat. The reconstituted wafer was then separated from the glass carrier through a laser ablation process using a 308-nm laser to complete the design of experiments (DOE). An experiment to study the correlation of glass carrier, laser release layer, build-up layers, and molding compound in RDL-first FOWLP processes is discussed to address full process integration on 300-mm glass substrates. The combination of glass carrier, laser release layer, build-up layer, and molding compound will pave the way for realizing cost-effective RDL-first FOWLP on panel-size substrates.

3D Process Integration – Wafer-to-Wafer and Chip-to-Wafer Bonding

2006 ◽  
Vol 970 ◽  
Author(s):  
Thorsten Matthias ◽  
Markus Wimplinger ◽  
Stefan Pargfrieder ◽  
Paul Lindner
Keyword(s):  
Wafer Bonding ◽  
Process Integration ◽  
Logic Device ◽  
Wafer Level ◽  
Integration Schemes ◽  
Research Level ◽  
Rf Devices ◽  
Manufacturing Technologies ◽  
The Individual ◽  
3D Chip Stacking

ABSTRACTMany feasibility and design studies during the last years have shown that devices based on 3D chip stacking and integration can significantly outperform traditional planar (2D) devices. Furthermore, as packaging of the devices is a major cost factor, the possibility to integrate multiple functional entities in one package offers a huge potential for cost reduction. On research level the technical feasibility has been proven for a variety of processes. Today's focus lies on innovative manufacturing technologies and process integration schemes, which meet both, the economic and the technical demands.Stacking of individual chips (both chip-to-wafer and wafer-to-wafer) has the inherent advantage that different functional subsystems like logic and memory can be processed on separate wafers thereby reducing the complexity and the number of process steps greatly. The individual chips can be processed on heterogeneous materials, in different fabs and by different producers.Wafer-level integration has the advantage of higher throughput, enhanced cleanliness and the flexibility that standard fab equipment can be used for further processing. 3D integration applying chip-to-wafer bonding focuses on the yield (“good known die”) and enables to stack dies of different size e.g. several small dies on one big base die. This allows e.g. the integration of a logic device from a 300mm Si wafer with RF devices from a 150mm GaAs wafer.In this paper a higher emphasis lies on the key enabling manufacturing technologies and supported processes.

Advanced lithography and electroplating approach to form high-aspect ratio copper pillars

2015 ◽  
Vol 2015 (1) ◽  
pp. 000793-000798
Author(s):  
Keith Best ◽  
Roger McCleary ◽  
Richard Hollman ◽  
Phillip Holmes
Keyword(s):  
Aspect Ratio ◽  
High Aspect Ratio ◽  
High Performance ◽  
Flip Chip ◽  
Technology Development ◽  
Semiconductor Industry ◽  
Scale Up ◽  
Wafer Level ◽  
Integration Schemes ◽  
Advanced Packaging

Advanced packaging technologies continue to enable the semiconductor industry to meet the needs for ever thinner, smaller and faster components required in mobile devices and other high performance applications. In the early days of advanced packaging, C4 solder bumps were the alternative to wire bonding. Although lead-free solder remains one of the preferred methods for assembly, tall copper structures (copper pillars) are becoming the standard interconnect solution for many applications. A process of lithography and subsequent electroplating are the mainstream process for today's copper pillar formation on wafer level for high-end flip chip devices. The latest trends in advanced packaging require another technology development when it comes to copper pillars. Modern integration schemes such as 2.5D interposer as well as 3D stacking have pushed the limits of standard lithography and copper electroplating capabilities. Specifically, the need for fine-pitch high aspect ratio copper pillars represents a challenge. In addition, the trend towards rectangular panel-based packaging as seen with glass interposers or panel fan-out (P-FO) devices demands a challenging scale-up of lithography and electroplating equipment and processing capabilities. This work specifically focuses on the formation of high-aspect ratio copper pillars in excess of 100μm by means of stepper-based lithography followed by electroplating. A unique test vehicle has been created to evaluate the process latitude for lithography for different resist materials as well as the specific electroplating challenges associated with these tall and narrow structures. The paper investigates the influence of key parameters such as CD uniformity, pattern density variations and resist profile on the critically important pillar height uniformity across the wafer or panel. In addition, the resist profile behavior at the substrate interface is being examined as it influences undercut behavior during wet etch of the plating seed layer. A number of wet and dry-film resist materials and appropriate lithography processes (spin coat or laminate, expose, develop) followed by copper plating based on varying chemistries and process parameters are being explored. The paper also summarizes the current requirements for the above mentioned lithography and plating processes as seen in the industry today.

Characterization of Unfilled Tungsten Plugs on a 0.35μm CMOS Multilevel Metallization Process

1996 ◽  
Author(s):  
H. Sur ◽  
S. Bothra ◽  
Y. Strunk ◽  
J. Hahn
Keyword(s):  
Process Development ◽  
Process Integration ◽  
Wafer Level ◽  
Electrical Failure ◽  
Analysis Techniques ◽  
Integration Approach ◽  
Intermetal Dielectric ◽  
Metallization Process ◽  
Section Analysis

Abstract An investigation into metallization/interconnect failures during the process development phase of an advanced 0.35μm CMOS ASIC process is presented. The corresponding electrical failure signature was electrical shorting on SRAM test arrays and subsequently functional/Iddq failures on product-like test vehicles. Advanced wafer-level failure analysis techniques and equipment were used to isolate and identify the leakage source as shorting of metal lines due to tungsten (W) residue which was originating from unfilled vias. Further cross-section analysis revealed that the failing vias were all exposed to the intermetal dielectric spin-on glass (SOG) material used for filling the narrow spaces between metal lines. The outgassing of the SOG in the exposed regions of the via prior to and during the tungsten plug deposition is believed to be the cause of the unfilled vias. This analysis facilitated further process development in eliminating the failure mechanism and since then no failures of this nature have been observed. The process integration approach used to eliminate the failure is discussed.

scholarly journals Challenges for Evaluation of the Safety of Engineered Nanomaterials

2021 ◽  
Vol 43 (1) ◽  
pp. 4-7
Author(s):  
Linda J. Johnston ◽  
Norma Gonzalez-Rojano ◽  
Kevin J. Wilkinson ◽  
Baoshan Xing
Keyword(s):  
Rapid Development ◽  
Sustainable Use ◽  
Cost Effective ◽  
Engineered Nanomaterials ◽  
Full Potential ◽  
Effective Strategies ◽  
Toxicological Studies ◽  
Regulatory Guidelines ◽  
Significant Effort ◽  
Safe By Design

Abstract Nanotechnology has developed rapidly in the last two decades with significant effort focused on the development of nano-enabled materials with new or improved properties that offer solutions for current world challenges. The commercialization of products containing engineered nanomaterials (ENM) has progressed much more rapidly than the development of practical approaches to ensure their safe and sustainable use. The lack of adequate detection and characterization techniques and reproducible and validated methods for toxicological studies have been identified as major limitations. The rapid development of ENM of increasing complexity and diversity and concerns over the adequacy of existing regulations also contribute to safety concerns with these materials. The full potential of nanotechnology can only be realized when feasible, cost-effective strategies to ensure a safe-by-design approach, effective risk assessment approaches and appropriate regulatory guidelines are in place.

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