dopant loss
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2019 ◽  
Vol 25 (5) ◽  
pp. 367-374
Author(s):  
Dunja Radisic ◽  
Denis Shamiryan ◽  
Geert Mannaert ◽  
Werner Boullart ◽  
Erik Rosseel ◽  
...  
Keyword(s):  

ACS Catalysis ◽  
2017 ◽  
Vol 7 (2) ◽  
pp. 1485-1490 ◽  
Author(s):  
Nicholas P. Chadwick ◽  
Andreas Kafizas ◽  
Raul Quesada-Cabrera ◽  
Carlos Sotelo-Vazquez ◽  
Salem M. Bawaked ◽  
...  

2013 ◽  
Vol 20 (03n04) ◽  
pp. 1350038 ◽  
Author(s):  
M. N. MESLI ◽  
B. BENBAHI ◽  
H. BOUAFIA ◽  
M. BELMEKKI ◽  
B. ABIDRI ◽  
...  

The aim of our investigation is focused on studying the effect of dopant dose loss during annealing treatments on heavily doped surface layers, obtained by recoil implantation of antimony in silicon. We are interested particularly by the increase of sheet resistance consequently to the shallow junctions obtained at the surface of substrate and the contribution of the dopant dose loss phenomenon following the high concentration of impurities at the surface. In this work, we report some quantitative data concerning the dopant loss at the surface of silicon implanted and its dependence with annealing treatments. Electrical measurements associated with Rutherford backscattering (RBS) technical analysis showed interesting values of sheet resistance compared with classical ion implantation and despite dopant dose loss phenomenon.


2012 ◽  
Vol 187 ◽  
pp. 41-44 ◽  
Author(s):  
Nick Valckx ◽  
Daniel Cuypers ◽  
Rita Vos ◽  
Harold Philipsen ◽  
Jens Rip ◽  
...  

Following Moores scaling law, the transistor source and drain area become shallower and higher doped regions. As a consequence the limitations of substrate and dopant loss during cleaning become more stringent. For a better understanding, highly B, As and P doped blanket substrates, either prepared by ion implantation or by EPI growth, are studied. Substrate and dopant loss as a function of time and different HF etching conditions is monitored by Inductively Coupled Plasma Mass Spectrometry (ICP-MS) and additional techniques like Spectroscopic Ellipsometry (SE), .... It is shown that in general, the Si etching is dependent of the position of the Fermi level. More remarkably, the junction (4 nm) of a non-annealed heavily As or P doped substrate is completely removed after less than 20 min of etching in HF. This process is related to enhanced etch rates because of the amorphization of the substrate.


2012 ◽  
Vol 187 ◽  
pp. 93-96 ◽  
Author(s):  
Shi Jian Luo ◽  
Orlando Escorcia ◽  
David Mattson ◽  
Carlo Waldfried ◽  
Dong Wan Roh ◽  
...  

Two alternative plasma strip processes were developed to meet the photoresist (PR) removal requirements of future technology nodes. Compared to traditional oxidizing chemistries, the new plasma strip approaches showed significantly lower silicon oxidation and substrate loss, while achieving good residue removal capabilities. Plasma strip-induced dopant loss and profile changes were also evaluated for gate-first and gate-last high-k/metal gate applications.


2009 ◽  
Vol 145-146 ◽  
pp. 253-256 ◽  
Author(s):  
G. Mannaert ◽  
L. Witters ◽  
Denis Shamiryan ◽  
Werner Boullart ◽  
K. Han ◽  
...  

The most advanced technology nodes require ultra shallow extension implants (low energy) which are very vulnerable to ash related substrate oxidation, silicon and dopant loss, which can result in a dramatic increase of the source/drain resistance and shifted transistor threshold voltages. A robust post extension ion implant ash process is required in order to meet cleanliness, near zero Si loss and dopant loss specifications. This paper discusses a performance comparison between fluorine-free, reducing and oxidizing, ash chemistries and “as implanted – no strip” process conditions, for both state-of-the-art nMOS and pMOS implanted fin resistors. Fluorine-free processes were chosen since earlier experiments with fluorine containing plasma strips exhibited almost a 10x increase in sheet resistance in the worse case.


2009 ◽  
Vol 145-146 ◽  
pp. 289-292 ◽  
Author(s):  
Stéphane Malhouitre ◽  
Rita Vos ◽  
Souvik Banerjee ◽  
Paul Cheng ◽  
Twan Bearda ◽  
...  

In FEOL processing, doping of active areas like source, drain, and extensions (NMOS and PMOS) is done by ion implantation. Un-doped regions are covered with photoresist to protect them from implantation. Ion implantation modifies the surface of the photoresist to generate a dehydrogenated amorphous carbon layer, the crust [1]. When the implant conditions are more aggressive (higher implant energy and implant dose), the hard crust becomes more and more challenging to be removed [2]. Conventionally, a plasma ashing process followed by a wet cleaning, typically SPM (Sulfuric acid/Hydrogen peroxide mixture) chemistry, can remove the implanted photoresist, but usually leads to damage and strong oxidation of the underlying semiconductor material and hence result in material or dopant loss. As the technology node migrates beyond 45nm, the photoresist removal process should also be compatible with novel materials such as high-k dielectric and metal-gate used in advanced gate stack integration. For these reasons, it is desirable to eliminate the plasma ash and SPM clean chemistry. Wet only PR removal process is studied using new chemistries like solvents that are compatible with the other FEOL process steps, however, the photoresist removal using solvents only still showed lower removal efficiency than conventional processes. It has been demonstrated that the CO2 cryogenic pre-treatment can improve the ion implanted photoresist stripping efficiency of the wet cleaning processes [3], and can also enhance the photoresist removal efficiency by the solvents.


2009 ◽  
Vol 145-146 ◽  
pp. 249-252 ◽  
Author(s):  
Ke Ping Han ◽  
S. Luo ◽  
O. Escorcia ◽  
Carlo Waldfried ◽  
Ivan L. Berry

High dose, ultra shallow junction implant resist strip requires minimal substrate loss and dopant loss. Silicon recess (silicon loss) under the source/drain (S/D) extensions increases the S/D extension resistance and decreases drive currents by changing the junction profile. ITRS surface preparation technology roadmap [1] targets silicon loss to be 0.4Å per cleaning step for 45nm and 0.3Å for 32nm generation. Fluorine-containing chemistries which are often used to enhance implanted resist strip and residue removal result in unacceptable substrate loss. A non-fluorine plasma strip was developed in earlier work and is qualified for 45nm logic production [2]. The objective of this work is to study the substrate damage that is induced by the resist strip plasma process. Silicon surface oxidation and silicon loss of different plasma strip chemistries were evaluated with various metrologies such as optical ellipsometry, electrical oxide measurement, XPS, TEM and mass measurement. The impact of different strip chemistries on dopant retention and distribution is also discussed.


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