Interpretation of Resistance Changes during Interconnect Reliability Testing

1994 ◽  
Vol 338 ◽  
Author(s):  
John E. Sanchez ◽  
Van Pham
Keyword(s):  
Joule Heating ◽  
Failure Criteria ◽  
Reliability Testing ◽  
High Current ◽  
Current Testing ◽  
Interconnect Test ◽  
Test Conditions ◽  
Interconnect Reliability ◽  
Initial Resistance ◽  
Improved Methods

ABSTRACTAccelerated reliability testing of VLSI layered metallizations involves monitoring the resistance of interconnect test structures under the assumption that changes in the resistance are due to processes (i.e., damage) which are induced by the test conditions (current and/or temperature.) “Failure” of the interconnect is defined as a somewhat arbitrary increase in fractional resistance ΔR/Ro ≈ +10% to +30%, where Ro is the initial resistance. However interpretation of the measured ΔR/Ro (both positive and negative) is complicated by other processes, the test conditions, and the test structure itself which all contribute to ΔR/Ro. We estimate the magnitude of intrinsic factors, such as vacancies and solute effects, as well as extrinsic factors, such as interconnect strain and voiding, on measured on ΔR/Ro. We also show that localized joule heating at voids (a mixed intrinsic + extrinsic effect) principally accounts for the large ΔR/Ro measured during electromigration (i.e., high current) testing. These results suggest improved methods for the detection of interconnect voids induced by the stresses of passivation confinement. We outline the considerations which allow for more rigorous failure criteria which are scalable to any metallization layer scheme, interconnect length and test condition. Finally, we discuss the interpretation of resistance changes at interlevel via structures.

The Microstructural Nature of Electromigration and Mechanical Stress Voids in Integratedcircuit Interconnect

1993 ◽  
Vol 309 ◽  
Author(s):  
Jamie H. Rose ◽  
Terry Spooner
Keyword(s):  
Grain Boundary ◽  
Integrated Circuit ◽  
Boundary Diffusion ◽  
Void Formation ◽  
Parallel Line ◽  
Relative Displacement ◽  
Test Conditions ◽  
Line Array ◽  
Interconnect Reliability ◽  
Diffusion Paths

AbstractIt is well known that stress and electromigration induced voiding is of major concern for integrated circuit interconnect reliability. However, there has been little systematiccharacterization of void morphology and crystallography in ever more technologically important narrow, “near-bamboo” conducting lines. Prior reports indicate thatvoids are typically wedge or slit shaped, with failure often associated with slit voids.Void face habit plane is most often reported to be {111}. Wedge and slit void morphology and crystallography have been studied in comb/serpentine and parallel line array test structures. In virtually all cases, void faces are {111} oriented. In contrast to earlier studies, intragranular wedge stress voids have been observed. All electromigration opens were due to slit voids; these were typically intragranular, in contradiction to current theories of void formation, and likely are mechanical fractures. Under accelerated test conditions, non-grain boundary diffusion paths appear to operate at distances of tens of micrometers. Relative displacement between wedge voids and attached grain boundaries occurs where a wedge face lies on a near common {111} plane for the two grains. It is suggested that slit voids are intragranular under both stress and electromigration conditions and likely associated with local interconnect depassivation. Based solely on appearance and crystallography, no void can uniquely be identified as due to stress alone or electromigration alone.

Thermal and Electrical Transport in Carbon Nanofiber Interconnects

2008 ◽  
Author(s):  
Tsutomu Saito ◽  
Hirohiko Kitsuki ◽  
Makoto Suzuki ◽  
Toshishige Yamada ◽  
Drazen Fabris ◽  
...  
Keyword(s):  
Heat Transport ◽  
Carbon Nanofibers ◽  
Joule Heating ◽  
Current Density ◽  
Electrical Transport ◽  
Heat Dissipation ◽  
Carbon Nanofiber ◽  
Transport Model ◽  
High Current ◽  
Current Stress

We study reliability of carbon nanofibers (CNFs) under high-current stress by examining CNF breakdown on four different configurations, suspended or supported, with/without tungsten deposition. The suspended results are consistently explained with a heat transport model taking into account Joule heating and heat dissipation along the CNF, while supported cases show a consistently larger current density just before breakdown, reflecting effective heat dissipation to the substrate.

Experimental Study of Damage Mechanism of Carbon Nanotube as Nanocomponent of Electronic Devices Under High Current Density

2014 ◽  
Vol 136 (4) ◽  
Author(s):  
Kazuhiko Sasagawa ◽  
Kazuhiro Fujisaki ◽  
Jun Unuma ◽  
Ryota Azuma
Keyword(s):  
Carbon Nanotubes ◽  
Joule Heating ◽  
Current Density ◽  
High Current Density ◽  
Damage Mechanism ◽  
Cathode Side ◽  
Testing System ◽  
High Current ◽  
Multiwalled Carbon ◽  
And Migration

The damage mechanisms of carbon nanotubes are considered to be the oxidation by Joule heating and migration of carbon atoms by high-density electron flows. In this study, a high current density testing system was designed and applied to multiwalled carbon nanotubes (MWCNTs) collected at the gap between thin-film electrodes. Local evaporation of carbon atoms occurred on the cathode side of the MWCNTs under relatively low current density conditions, and the center area of the MWCNTs under high current density conditions. The damaged morphology could be explained by considering both Joule heating and electromigration behavior of MWCNTs.

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