Effects of Inversion Layer Quantization and Polysilicon Gate Depletion on Tunneling Current of Ultra-Thin SiO2 Gate Material

1999 ◽  
Vol 567 ◽  
Author(s):  
S. Saha ◽  
G. Srinivasan ◽  
G. A. Rezvani ◽  
M. Farr
Keyword(s):  
Leakage Current ◽  
Supply Voltage ◽  
Inversion Layer ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Gate Leakage Current ◽  
Gate Leakage ◽  
Polysilicon Gate ◽  
Gate Oxide Thickness ◽  
The Impact

ABSTRACTWe have investigated the impact of inversion layer quantization and polysilicon-gate depletion effects on the direct-tunneling gate-leakage current and reliability of ultra-thin silicon-dioxide gate dielectric. The gate-leakage current was measured for nMOSFET devices with gate oxide thickness down to 3 nm. A simulation-based methodology was used to determine the physical oxide thickness from the measured capacitance data, and the corresponding effective gate oxide thickness at inversion was computed from the simulation data obtained with and without the quantum mechanical and polysilicon depletion effects. The simulation results indicate that the effective gate oxide thickness is significantly higher than the physically grown oxide thickness due to inversion layer quantization and polysilicon depletion effects. The increase in oxide thickness is strongly dependent on the supply voltage and is more than 0.6 nm at 1 V. Our data, also, show that in order to maintain a leakage current ≥ 1 A/cm2 for 1 V operation, the effective gate oxide thickness must be ≥ 2.2 nm.

Correlation Between Gate Induced Drain Leakage and Plasma Induced Interface Traps

1999 ◽  
Vol 592 ◽  
Author(s):  
Siguang Ma ◽  
Yaohui Zhang ◽  
M. F. Li ◽  
Weidan Li ◽  
J. L. F. Wang ◽  
...  
Keyword(s):  
Leakage Current ◽  
Field Enhancement ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Deep Submicron ◽  
Interface Traps ◽  
Low Field ◽  
Polysilicon Gate ◽  
Gate Oxide Thickness ◽  
Thin Gate Oxide

ABSTRACTIn this paper we carefully investigate the correlation between gate induced drain leakage current and plasma induced damages in the deep submicron p+ polysilicon gate pMOSFETs with gate oxide thickness of 50 Å. Low field enhancement of gate induced drain leakage current caused by plasma charging damage is a function of metal 1 antenna area/length ratio and cell location. Combined with the charge pumping measurements, it is found that gate induced drain leakage current enhancement is mainly due to the plasma induced interface traps. A linear relationship between the gate induced drain leakage and the plasma induced interface trap density is observed within the experimental error. On the other hand, the threshold voltage measurements show that oxide trapped charge has no major contribution to, and no correlation with, the gate induced drain leakage current for thin gate oxide MOSFET devices.

scholarly journals Atomic-scale ferroic HfO2-ZrO2 superlattice gate stack for advanced transistors

2021 ◽  
Author(s):  
Suraj Cheema ◽  
Nirmaan Shanker ◽  
Li-Chen Wang ◽  
Cheng-Hsiang Hsu ◽  
Shang-Lin Hsu ◽  
...  
Keyword(s):  
Leakage Current ◽  
High Performance ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Atomic Scale ◽  
Oxide Semiconductor ◽  
Operating Voltage ◽  
Gate Stacks ◽  
Gate Stack ◽  
Gate Oxide Thickness

Abstract With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage. This led to the adoption of high-κ dielectric HfO2 in the gate stack in 2008, which remains as the material of choice to date. Here, we report HfO2-ZrO2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric-antiferroelectric order, directly integrated onto Si transistors and scaled down to ~ 20 Å, the same gate oxide thickness required for high performance transistors. The overall EOT (equivalent oxide thickness) in metal-oxide-semiconductor capacitors is equivalent to ~ 6.5 Å effective SiO2 thickness, which is, counterintuitively, even smaller than the interfacial SiO2 thickness (8.0-8.5 Å) itself. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO2-based high-κ dielectric gate stacks without scavenging the interfacial SiO2, which has adverse effects on the electron transport and gate leakage current. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. Therefore, our work demonstrates that HfO2-ZrO2 multilayers with competing ferroelectric-antiferroelectric order, stabilized in the 2 nm thickness regime, provides a new path towards advanced gate oxide stacks in electronic devices beyond the conventional HfO2-based high-κ dielectrics.

In-Line Monitor Introduction to Prevent Metallic Contamination in Wet Bench

2005 ◽  
Vol 108-109 ◽  
pp. 637-642 ◽  
Author(s):  
Domenico Mello ◽  
Francesco Cordiano ◽  
Andrea Gerosa ◽  
Margherita Padalino ◽  
Carmelo Gagliano ◽  
...  
Keyword(s):  
Flash Memory ◽  
Production Line ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Contamination Level ◽  
Process Flow ◽  
Gate Oxide Thickness ◽  
Metallic Contaminants ◽  
The Impact ◽  
Metallic Contamination

Contamination controls are very important issues in microelectronics. Any wrong substance introduction in process chambers can cause damages to the production line. Therefore, an extensive control is important because every operation in the process flow (also the most insignificant) can become fatal for the correct functioning of a microelectronic device. The aim of this work is to evaluate the impact of small metallic contamination in the range of 1011÷1012 at/cm2 on silicon substrates implanted with different ion species (As, B and P). An important example of failure related to metallic contamination in a wet bench is reported in this work. The problem appears in a particular class of flash memory devices processing. The electrical parametric test shows a wrong gate oxide thickness and Qbd values out of range, confirmed by early breakdown events and anomalous C-V characteristics. The cause of the failure is morphologically identified off-line by using TEM: the cross section shows a wrong gate oxide thickness and an anomalous interface between gate oxide and silicon substrate. It appears clear that the root failure cause is related to the ion implantation (As in this case) and to the cleaning before gate oxide growth. A short process flow was performed and analyzed step by step in order to identify the failure cause. Many different analytical techniques have been used for each step and all of these provide consistent results. In particular TXRF analysis on wafers processed immediately after cleaning do not show any contamination while Cu and Fe contaminants are observed after sample oxidation and As implant. Metallic contaminants are captured by the substrate after it is implanted with As, and the following RCA cleaning is not able to remove them. In addition, the presence of these metallic contaminants induces roughness of the Si surface and the growth of gate oxide is not controlled (faster oxidation). If different substrates are used, e.g. silicon implanted with B or un-implanted, this contamination level is not detected and does not lead to oxide reliability problems. Once the mechanism of metal contaminant interaction with dopant is identified the introduction of an in-line monitoring is possible, thus allowing to prevent the device failure. The short process loop can be considered as a good method to prepare the substrate before TXRF analysis. After this study the monitor has been integrated in the production line controls

Stress-induced high-field gate leakage current in ultra-thin gate oxide

2000 ◽  
Vol 44 (6) ◽  
pp. 977-980 ◽  
Author(s):  
Jianlin Wei ◽  
Lingfeng Mao ◽  
Mingzhen Xu ◽  
Changhua Tan ◽  
Xiaorong Duan
Keyword(s):  
Leakage Current ◽  
High Field ◽  
Gate Oxide ◽  
Gate Leakage Current ◽  
Gate Leakage ◽  
Thin Gate Oxide
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