Ultrathin Gate Oxides with Shallow Nitrogen Implants as Effective Barriers to Boron Diffusion

1999 ◽  
Vol 567 ◽  
Author(s):  
Yoshi Ono ◽  
Yanjun Ma ◽  
Sheng-Teng Hsu

ABSTRACTPlasma immersion ion implantation (PIII) has been employed to controllably place nitrogen ions from an inductively coupled plasma into a thin furnace grown gate oxide 2.0nm thick with implant voltages from 25 to 500V. Control of the implant energy enables shallow implantation confining the nitrogen mainly within the oxide. Rapid thermal annealing is essential in repairing any damage to the implanted silicon dioxide and silicon while consolidating the bonding of nitrogen into the oxide film prior to gate polysilicon deposition. High frequency capacitance-voltage measurements of capacitors made with BF2+ implanted gates throughout a series of furnace anneals demonstrates the efficiency for blocking boron compared to non-nitrided oxides of similar thickness. Tddb measurements verify excellent reliability compared to a non-implanted oxide for both stress polarities.

1993 ◽  
Vol 303 ◽  
Author(s):  
Bojun Zhang ◽  
Dennis M. Maher ◽  
Mark S. Denker ◽  
Mark A. Ray

ABSTRACTWe report a systematic study of dopant diffusion behavior for thin gate oxides and polysilicon implanted gate structures. Boron behavior is emphasized and its behavior is compared to that of As+ and BF2+. Dopant activation is achieved by rapid thermal annealing. Test structures with 100 Å, 60 Å and 30 Å gate oxides and ion implanted polysilicon gate electrodes were fabricated and characterized after annealing by SIMS, SEM, TEM, and C-V rpeasurements. For arsenic implanted structures, no dopant diffusion through a gate oxide of 30 Å thickness and an annealing condition as high as 1 100*C/1Os was observed. For boron implanted structures, as indicated by SIMS depth profiling, structures annealed at 1000*C/10s exhibit a so-called critical condition for boron diffusion through a 30 Å gate oxide. Boron dopant penetration is clearly observed for 60 Å gate oxides at an annealing condition of 1050 0C/10s. The flatband voltage shift can be as high as 0.56 volts as indicated by C-V measurements for boron penetrated gate oxides. However, 100 Å gate oxides are good diffusion barriers for boron at an annealing condition of 1100°C/10s. For BF2 implanted structures, the diffusion behavior is consistent with behavior reported in the literature.


1999 ◽  
Vol 573 ◽  
Author(s):  
J. W. Lee ◽  
K. D. Mackenzie ◽  
D. Johnson ◽  
S. J. Pearton ◽  
F. Ren ◽  
...  

ABSTRACTHigh-density plasma technology is becoming increasingly attractive for the deposition of dielectric films such as silicon nitride and silicon dioxide. In particular, inductively-coupled plasma chemical vapor deposition (ICPCVD) offers a great advantage for low temperature processing over plasma-enhanced chemical vapor deposition (PECVD) for a range of devices including compound semiconductors. In this paper, the development of low temperature (< 200°C) silicon nitride and silicon dioxide films utilizing ICP technology will be discussed. The material properties of these films have been investigated as a function of ICP source power, rf chuck power, chamber pressure, gas chemistry, and temperature. The ICPCVD films will be compared to PECVD films in terms of wet etch rate, stress, and other film characteristics. Two different gas chemistries, SiH4/N2/Ar and SiH4/NH3/He, were explored for the deposition of ICPCVD silicon nitride. The ICPCVD silicon dioxide films were prepared from SiH4/O2/Ar. The wet etch rates of both silicon nitride and silicon dioxide films are significantly lower than films prepared by conventional PECVD. This implies that ICPCVD films prepared at these low temperatures are of higher quality. The advanced ICPCVD technology can also be used for efficient void-free filling of high aspect ratio (3:1) sub-micron trenches.


2007 ◽  
Vol 989 ◽  
Author(s):  
Ming He ◽  
R. Ishihara ◽  
T. Chen ◽  
J.W. Metselaar ◽  
C.I.M. Beenakker

AbstractSingle grain TFTs are fabricated at a maximum temperature of 100oC for macroelectronics on a plastic substrate, as Si channels are fabricated at 100oC by combination of excimer laser crystallization and sputtering. The gate oxide is formed at 80°C by inductively coupled plasma enhanced chemical vapor deposition. These TFTs have shown a smaller threshold swing of 0.49 V/dec. and a higher field-effect mobility of 290 cm2/V·s, which can be used to directly fabricate system circuits or a high quality display on a plastic substrate.


2007 ◽  
Vol 46 (8A) ◽  
pp. 5304-5312 ◽  
Author(s):  
Hideo Kitagawa ◽  
Masamichi Uehara ◽  
Yusuke Fukuchi ◽  
Nobumasa Suzuki

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