scholarly journals DESIGN OPTIMIZATION OF EXTREMELY SHORT-CHANNEL GRADED SI/SIGE HETEROJUNCTION TUNNEL FIELD-EFFECT TRANSISTORS FOR LOW POWER APPLICATIONS

2018 ◽  
Vol 51 (6) ◽  
pp. 757
Author(s):  
Nguyen Dang Chien

This study investigates, by a two-dimensional simulation, the design optimization of a proposed 8 nm tunnel field-effect transistor (TFET) for low standby power (LSTP) applications utilizing graded Si/SiGe heterojunction with device parameters based on the ITRS specifications. The source Ge mole fraction should be designed approximately 0.8 because using lower Ge fractions causes severe short-channel effects while with higher values does not significantly improve the device performance but may create big difficulties in fabrication. Based on simultaneously optimizing the subthreshold swing, on- and off-currents, optimum values of source doping, drain doping and length of the proposed device are approximately 1020 cm-3,                1018 cm-3, and 10 nm, respectively. The 8 nm graded Si/SiGe TFET with optimized device parameters demonstrates high on-current of 360 μA/μm, low off-current of 0.5 pA/μm, low threshold voltage of 85 mV and very steep subthreshold swing of sub-10 mV/decade. The designed TFET with graded Si/SiGe heterojunction exhibits an excellent performance and makes it an attractive candidate for future LSTP technologies because of its reality to be fabricated with existing FET and SiGe growth techniques.

Author(s):  
Raj Kumar ◽  
Shashi Bala ◽  
Arvind Kumar

To have enhanced drive current and diminish short channel effects, planer MOS transistors have migrated from single-gate devices to three-dimensional multi-gate MOSFETs. The gate-all-around nanowire field-effect transistor (GAA NWFET) and nanotube or double gate-all-around field-effect transistors (DGGA-NTFET) have been proposed to deal with short channel effects and performance relates issues. Nanowire and nanotube-based field-effect transistors can be considered as leading candidates for nanoscale devices due to their superior electrostatic controllability, and ballistic transport properties. In this work, the performance of GAA NWFETs and DGAA-NT FETs will be analyzed and compared. III-V semiconductor materials as a channel will also be employed due to their high mobility over silicon. Performance analysis of junctionless nanowire and nanotube FETs will also be compared and presented.


2012 ◽  
Vol 67 (6-7) ◽  
pp. 317-326 ◽  
Author(s):  
Alireza Heidari ◽  
Niloofar Heidari ◽  
Foad Khademi Jahromi ◽  
Roozbeh Amiri ◽  
Mohammadali Ghorbani

In this paper, first, the impact of different gate arrangements on the short-channel effects of carbon nanotube field-effect transistors with doped source and drain with the self-consistent solution of the three-dimensional Poisson equation and the Schr¨odinger equation with open boundary conditions, within the non-equilibrium Green function, is investigated. The results indicate that the double-gate structure possesses a quasi-ideal subthreshold oscillation and an acceptable decrease in the drain induced barrier even for a relatively thick gate oxide (5 nm). Afterward, the electrical characteristics of the double-gate carbon nanotube field-effect transistors (DG-CNTFET) are investigated. The results demonstrate that an increase in diameter and density of the nanotubes in the DG-CNTFET increases the on-state current. Also, as the drain voltage increases, the off-state current of the DG-CNTFET decreases. In addition, regarding the negative gate voltages, for a high drain voltage, increasing in the drain current due to band-to-band tunnelling requires a larger negative gate voltage, and for a low drain voltage, resonant states appear


2005 ◽  
Author(s):  
Joshua N. Haddock ◽  
Xiaohong Zhang ◽  
Shijun Zheng ◽  
Seth R. Marder ◽  
Bernard Kippelen

2012 ◽  
Vol 2012 ◽  
pp. 1-7 ◽  
Author(s):  
Ali Naderi ◽  
S. Mohammad Noorbakhsh ◽  
Hossein Elahipanah

By developing a two-dimensional (2D) full quantum simulation, the attributes of carbon nanotube field-effect transistors (CNTFETs) in different temperatures have been comprehensively investigated. Simulations have been performed by employing the self-consistent solution of 2D Poisson-Schrödinger equations within the nonequilibrium Green's function (NEGF) formalism. Principal characteristics of CNTFETs such as current capability, drain conductance, transconductance, and subthreshold swing (SS) have been investigated. Simulation results present that as temperature raises from 250 to 500 K, the drain conductance and on-current of the CNTFET improved; meanwhile the on-/off-current ratio deteriorated due to faster growth in off-current. Also the effects of temperature on short channel effects (SCEs) such as drain-induced barrier lowering (DIBL) and threshold voltage roll-off have been studied. Results show that the subthreshold swing and DIBL parameters are almost linearly correlated, so the degradation of these parameters has the same origin and can be perfectly influenced by the temperature.


2021 ◽  
Author(s):  
Tulika Chawla ◽  
Mamta Khosla ◽  
Balwinder Raj ◽  
Sanjeev Kumar Sharma

This paper reviews the development of various structures of Tunnel Field Effect Transistors. In order to enhance the on-state current and decrease the short-channel effects, various non-planar structures were designed. Among all these non-planar structures, DGDM-GeOI Vertical TFET structure not only provide the benefits of performance enhancement but also fulfill the requirement of reduced footprint of the device.


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