Design of a Low Power Two Stage Operational Amplifier using MT-CMOS Technology: A New Approach

A phase margin symbolic expression of a two stage Miller compensated operational amplifier is computed in this paper. Using this expression, an analysis to evaluate the influence of the Miller and load capacitance on phase margin is performed. This way, a designer can rapidly choose the optimal set of values to fulfil an imposed phase margin. The phase margin expression is based on poles/zeros symbolic expressions obtained using a symbolic LR algorithm able to compute both the numerical values and the approximate symbolic expressions of poles and zeros of a circuit. The numerical values obtained with this algorithm are compared with those computed by SPECTRE. The example is a two stage Miller compensated operational amplifier designed in a 180nm CMOS technology.

Download Full-text

A Low-Noise Biopotential CMOS Amplifier IC Using Low-Power Two-Stage OTA for Neural Recording Applications

Journal of Circuits System and Computers ◽

10.1142/s0218126618500688 ◽

2018 ◽

Vol 27 (05) ◽

pp. 1850068 ◽

Cited By ~ 6

Author(s):

Hyung Seok Kim ◽

Hyouk-Kyu Cha

Keyword(s):

Low Power ◽

Integrated Circuit ◽

Cmos Technology ◽

Neural Recording ◽

Open Loop ◽

Low Noise ◽

Two Stage ◽

Prosthetic Devices ◽

Transconductance Amplifier ◽

Cmos Amplifier

This work presents a low-power biopotential amplifier integrated circuit (IC) for implantable neural recording prosthetic devices which have been implemented using 0.18-[Formula: see text]m CMOS technology. The proposed neural recording amplifier is based on a capacitive-feedback architecture and utilizes a low-power two-stage source-degenerated operational transconductance amplifier (OTA) with a modified current buffer compensation for large open-loop gain, low-noise and wide bandwidth. The designed amplifier achieves a measured gain of 39.2[Formula: see text]dB with a bandwidth between 0.25[Formula: see text]Hz to 28[Formula: see text]kHz, integrated input referred noise of 5.79[Formula: see text][Formula: see text]Vrms and noise efficiency factor of 3.16. The IC consumes 2.4[Formula: see text][Formula: see text]W at 1.2[Formula: see text]V supply and the die area is 0.09[Formula: see text]mm2.

Download Full-text

Design of Low Power, High Gain Fully Differential Folded Cascode Operational Amplifier for Front End Read Out Circuits

International Journal of Recent Technology and Engineering - 2 ◽

10.35940/ijrte.c6189.118419 ◽

2019 ◽

Vol 8 (4) ◽

pp. 1802-1808

Keyword(s):

Integrated Circuits ◽

Low Power ◽

Operational Amplifier ◽

Cmos Technology ◽

High Gain ◽

Vital Role ◽

Open Loop ◽

Fully Differential ◽

Front End ◽

Folded Cascode

The Front end read out circuits are major block in the implementation of Capacitive MEMS accelerometer. Front end read-out circuits comprises of preamplifier block containing folded cascode fully differential operational amplifier which are required for the signal conditioning of the signals received from the MEMS sensors. The op-amps are prime elements in design and implementation of mixed signal integrated circuits. The high gain and low power of the designed circuits helps in the designing of high precision IC’s for numerous application. Amongst the available topologies folded cascode topology plays vital role in the design and development of low power, high gain read out circuits. This paper illustrates the design and analysis of low power, high gain fully differential Folded Cascode Operational Amplifier for front end read out circuits. The designed op-amp exhibits a power consumption or dissipation of 92.14 μW and relatively higher open loop DC gain value with a value calculated at 81.33 dB by employing folded cascode topology. The UGB and Phase Margin for the selected design are 35 MHz and 83.60 respectively. The design operates at 5V power supply with the bias current of 12.11 μA. The circuit design and simulations have been implemented using 0.18 μm CMOS technology.

Download Full-text