Design and Analysis of a Low-Power Two-Stage Dynamic Comparator with 40ps Delay in 65nm CMOS Technology

2021 ◽  
Author(s):  
Razieh Ghasemi ◽  
Hossein Ghasemian ◽  
Ebrahim Abiri ◽  
Mohammad Reza Salehi
Keyword(s):  
Low Power ◽  
Cmos Technology ◽  
Two Stage ◽  
Dynamic Comparator

Contemporary Low Power Design Approaches

2016 ◽  
pp. 101-127
Author(s):  
Lini Lee
Keyword(s):  
Low Power ◽  
Vlsi Design ◽  
Low Power Design ◽  
Cmos Technology ◽  
Simulation Tool ◽  
Bandgap Reference ◽  
Voltage Level ◽  
Dynamic Comparator ◽  
Reference Circuit ◽  
Level Shifter

This chapter describes three contemporary low power design approaches; a resistor-less bandgap reference circuit, a hybrid voltage level shifter with a diode connected NMOS and a modified dynamic comparator, each design with the objective to demonstrate the feasibility of contemporary approaches in achieving lower power VLSI design. All three designs are simulated in 0.18 µm CMOS technology using industrial simulation tool and the results are based on performance parameters defined in the chapter.

scholarly journals Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation

2020 ◽  
Vol 17 (2) ◽  
pp. 783
Author(s):  
Julie Roslita Rusli ◽  
Suhaidi Shafie ◽  
Roslina Mohd Sidek ◽  
Hasmayadi Abdul Majid ◽  
W. Z. Wan Hassan ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Temperature Variation ◽  
Low Voltage ◽  
Cmos Technology ◽  
Worst Case ◽  
Dynamic Comparator ◽  
Analog To Digital ◽  
Power Dynamic ◽  
Voltage Supply

Power consumption and speed are the main criteria in designing comparator for analog-to-digital converter (ADC).  This paper presents an optimized low voltage low power dynamic comparator which is robust to process, voltage and temperature (PVT) variations with adequate speed.  The comparator circuit was designed using 0.18µm CMOS technology with low voltage supply of 0.8V.  The method used to verify the robustness of the comparator circuit across 45 PVT is presented.  The circuit is simulated with 10% voltage supply variation, five process corners and temperature variation from 0°C to 100°C. The simulation result show that the proposed comparator circuit achieved significant reduction of power consumption and delay during worst case condition compared to dynamic comparator proposed from previous researchers.

A Low-Noise Biopotential CMOS Amplifier IC Using Low-Power Two-Stage OTA for Neural Recording Applications

2018 ◽  
Vol 27 (05) ◽  
pp. 1850068 ◽  
Author(s):  
Hyung Seok Kim ◽  
Hyouk-Kyu Cha
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Cmos Technology ◽  
Neural Recording ◽  
Open Loop ◽  
Low Noise ◽  
Two Stage ◽  
Prosthetic Devices ◽  
Transconductance Amplifier ◽  
Cmos Amplifier

This work presents a low-power biopotential amplifier integrated circuit (IC) for implantable neural recording prosthetic devices which have been implemented using 0.18-[Formula: see text]m CMOS technology. The proposed neural recording amplifier is based on a capacitive-feedback architecture and utilizes a low-power two-stage source-degenerated operational transconductance amplifier (OTA) with a modified current buffer compensation for large open-loop gain, low-noise and wide bandwidth. The designed amplifier achieves a measured gain of 39.2[Formula: see text]dB with a bandwidth between 0.25[Formula: see text]Hz to 28[Formula: see text]kHz, integrated input referred noise of 5.79[Formula: see text][Formula: see text]Vrms and noise efficiency factor of 3.16. The IC consumes 2.4[Formula: see text][Formula: see text]W at 1.2[Formula: see text]V supply and the die area is 0.09[Formula: see text]mm2.

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