scholarly journals Influence of Back Contact Annealing Temperature in the mc-Si Solar Cell Fabrication Process

2021 ◽  
Author(s):  
Aravindan Gurusamy ◽  
S. Sanmugavel ◽  
S. G. Nagarajan ◽  
V. Kesavan ◽  
M. Sriniv ◽  
...  
Keyword(s):  
Annealing Temperature ◽  
Crystalline Silicon ◽  
Solidification Process ◽  
Minority Carrier Lifetime ◽  
Open Circuit ◽  
Fabrication Process ◽  
Back Contact ◽  
Doping Density ◽  
Boron Doped ◽  
Ar Coating

Abstract The boron doped multi-crystalline silicon (mc-Si) ingot was grown using the directional solidification process. Grown ingots were converted into bricks and then to wafers. We have fabricated silicon solar cells from the multi-crystalline silicon wafers. The minority carrier lifetime of the wafers is around 15-25 ms. Annealing was made after back and front contact during the fabrication process. The effect of back contact annealing temperature has been investigated. Annealing the device at 5830C for 5 sec gives better results. Typical open circuit voltage (Voc) of the devices is around ~540-550mV. The best cell had a power conversion efficiency of ~9 % with a typical acceptor doping density ~ 2.35 E+15 per cm3 (The devices reported here do not have AR coating layer, no passivation was done and the surfaces are also not textured).

scholarly journals Properties of Arsenic–Doped ZnTe Thin Films as a Back Contact for CdTe Solar Cells

Materials ◽  
2019 ◽  
Vol 12 (22) ◽  
pp. 3706 ◽  
Author(s):  
Ochai Oklobia ◽  
Giray Kartopu ◽  
Stuart J. C. Irvine
Keyword(s):  
Thin Films ◽  
Solar Cells ◽  
Open Circuit ◽  
Activation Process ◽  
Back Contact ◽  
Contact Activation ◽  
Doping Density ◽  
Cdte Solar Cells ◽  
Absorber Doping ◽  
P Type

As-doped polycrystalline ZnTe layers grown by metalorganic chemical vapor deposition (MOCVD) have been investigated as a back contact for CdTe solar cells. While undoped ZnTe films were essentially insulating, the doped layers showed significant rise in conductivity with increasing As concentration. High p-type carrier densities up 4.5 × 1018 cm−3 was measured by the Hall-effect in heavily doped ZnTe:As films, displaying electrical properties comparable to epitaxial ZnTe single crystalline thin films in the literature. Device incorporation with as-deposited ZnTe:As yielded lower photovoltaic (PV) performance compared to reference devices, due to losses in the open-circuit potential (VOC) and fill factor (FF) related to reducing p-type doping density (NA) in the absorber layer. Some minor recovery observed in absorber doping following a Cl-free post–ZnTe:As deposition anneal in hydrogen at 420 °C contributed to a slight improvement in VOC and NA, highlighting the significance of back contact activation. A mild CdCl2 activation process on the ZnTe:As back contact layer via a sacrificial CdS cap layer has been assessed to suppress Zn losses, which occur in the case of standard CdCl2 anneal treatments (CHT) via formation of volatile ZnCl2. The CdS sacrificial cap was effective in minimising the Zn loss. Compared to untreated and non-capped, mild CHT processed ZnTe:As back contacted devices, mild CHT with a CdS barrier showed the highest recovery in absorber doping and an ~10 mV gain in VOC, with the best cell efficiency approaching the baseline devices.

Interdigitated Back Contact Silicon Heterojunction (IBC-SHJ) Solar Cell

2007 ◽  
Vol 989 ◽  
Author(s):  
Meijun Lu ◽  
Stuart Bowden ◽  
Ujjwal Das ◽  
Michael Burrows ◽  
Robert Birkmire
Keyword(s):  
Surface Passivation ◽  
Crystalline Silicon ◽  
Spectral Response ◽  
Chemical Vapor ◽  
Front Surface ◽  
Minority Carrier Lifetime ◽  
Back Contact ◽  
Cell Structures ◽  
Current Voltage ◽  
Low Temperature Processing

AbstractInterdigitated back contact silicon heterojunction (IBC-SHJ) solar cells have been developed. This structure has interdigitated p/n amorphous silicon (a-Si:H) films deposited by plasma enhanced chemical vapor deposition (PECVD) on the backside of crystalline silicon (c-Si) wafers, with light irradiating the front surface. IBC-SHJ cells possess advantages over front junction a-Si:H/c-Si heterojunction cells due to minimized current losses in the illuminating side, and over traditional diffused back-junction cells due to low temperature processing combined with the potential of high voltages for the heterojunction. Current-voltage curves, spectral response and laser beam induced current maps have been used to characterize the IBC-SHJ cells. It was found that the IBC-SHJ cell has non-linear illumination level dependence that correlates with effective minority-carrier lifetime. As the performance of these cells is very sensitive to the quality of passivation on front surface, they are ideally suited as a diagnostic tool for detail characterization of surface passivation. Initial cell structures have achieved independently confirmed cell efficiencies of 11.8% under AM1.5 illumination. Device simulation shows an efficiency of higher than 20% can be expected after optimizing the IBC-SHJ cells.

Passivation of Silicon Surfaces by Treatment in Water at 110°C

2015 ◽  
Vol 1770 ◽  
pp. 37-42 ◽  
Author(s):  
Tomohiko Nakamura ◽  
Toshiyuki Sameshima ◽  
Masahiko Hasumi ◽  
Tomohisa Mizuno
Keyword(s):  
Solar Cell ◽  
Liquid Water ◽  
Crystalline Silicon ◽  
Surface Recombination ◽  
Minority Carrier Lifetime ◽  
Open Circuit ◽  
Silicon Surfaces ◽  
Silicon Substrates ◽  
Light Illumination ◽  
P Type

ABSTRACTWe report effective passivation of silicon surfaces by heating single crystalline silicon substrates in liquid water at 110°C for 1 h. High values of photo-induced effective minority carrier lifetime τeff in the range from 1.9x10-4 to 1.8x10-3 s were obtained for the n-type samples with resistivity in the range from 1.7 to 18.1 Ωcm. τeff ranged from 8.3x10-4 to 3.1x10-3 s and from 1.2x10-4 to 6.0x10-4 s over the area of 4 inch sized 17.0 Ωcm n- and 15.0 Ωcm p-type samples, respectively. The heat treatment in liquid water at 110°C for 1 h resulted in low surface recombination velocities ranging from 7 to 34 cm/s and from 49 to 250 cm/s for those 4 inch sized n- and p-type samples, respectively. The thickness of the passivation layer was estimated to be approximate only 0.7 nm. Metal-insulator-semiconductor type solar cell was demonstrated with Al and Au metal formation on the passivated surface. Rectified current voltage and solar cell characteristics were observed. Open circuit voltage of 0.47 V was obtained under AM 1.5 light illumination at 100 mW/cm2.

scholarly journals Microstructure and Mechanical Properties of Novel Quasibinary Al-Cu-Yb and Al-Cu-Gd Alloys

Metals ◽  
2021 ◽  
Vol 11 (3) ◽  
pp. 476
Author(s):  
Sayed Amer ◽  
Ruslan Barkov ◽  
Andrey Pozdniakov
Keyword(s):  
Mechanical Properties ◽  
Tensile Properties ◽  
Mechanism Of Action ◽  
Annealing Temperature ◽  
Eutectic Reaction ◽  
Solidification Process ◽  
Annealed State ◽  
Microstructure And Mechanical Properties ◽  
Cold Rolled ◽  
Hot Rolled

Microstructure of Al-Cu-Yb and Al-Cu-Gd alloys at casting, hot-rolled -cold-rolled and annealed state were observed; the effect of annealing on the microstructure was studied, as were the mechanical properties and forming properties of the alloys, and the mechanism of action was explored. Analysis of the solidification process showed that the primary Al solidification is followed by the eutectic reaction. The second Al8Cu4Yb and Al8Cu4Gd phases play an important role as recrystallization inhibitor. The Al3Yb or (Al, Cu)17Yb2 phase inclusions are present in the Al-Cu-Yb alloy at the boundary between the eutectic and aluminum dendrites. The recrystallization starting temperature of the alloys is in the range of 250–350 °C after rolling with previous quenching at 590 and 605 °C for Al-Cu-Yb and Al-Cu-Gd, respectively. The hardness and tensile properties of Al-Cu-Yb and Al-Cu-Gd as-rolled alloys are reduced by increasing the annealing temperature and time. The as-rolled alloys have high mechanical properties: YS = 303 MPa, UTS = 327 MPa and El. = 3.2% for Al-Cu-Yb alloy, while YS = 290 MPa, UTS = 315 MPa and El. = 2.1% for Al-Cu-Gd alloy.

Carrier Lifetime Measurements by Photoconductance at Low Temperature on Passivated Crystalline Silicon Wafers

2013 ◽  
Vol 1536 ◽  
pp. 119-125 ◽  
Author(s):  
Guillaume Courtois ◽  
Bastien Bruneau ◽  
Igor P. Sobkowicz ◽  
Antoine Salomon ◽  
Pere Roca i Cabarrocas
Keyword(s):  
Low Temperature ◽  
Electron Mobility ◽  
Carrier Density ◽  
Carrier Lifetime ◽  
Minority Carrier ◽  
Crystalline Silicon ◽  
Silicon Wafers ◽  
Doping Density ◽  
Lifetime Measurements ◽  
Effective Lifetime

ABSTRACTWe propose an implementation of the PCD technique to minority carrier effective lifetime assessment in crystalline silicon at 77K. We focus here on (n)-type, FZ, polished wafers passivated by a-Si:H deposited by PECVD at 200°C. The samples were immersed into liquid N2 contained in a beaker placed on a Sinton lifetime tester. Prior to be converted into lifetimes, data were corrected for the height shift induced by the beaker. One issue lied in obtaining the sum of carrier mobilities at 77K. From dark conductance measurements performed on the lifetime tester, we extracted an electron mobility of 1.1x104 cm².V-1.s-1 at 77K, the doping density being independently calculated in order to account for the freezing effect of dopants. This way, we could obtain lifetime curves with respect to the carrier density. Effective lifetimes obtained at 77K proved to be significantly lower than at RT and not to depend upon the doping of the a-Si:H layers. We were also able to experimentally verify the expected rise in the implied Voc, which, on symmetrically passivated wafers, went up from 0.72V at RT to 1.04V at 77K under 1 sun equivalent illumination.

17.8%-efficient Amorphous Silicon Heterojunction Solar Cells on p-type Silicon Wafers

2006 ◽  
Vol 910 ◽  
Author(s):  
Qi Wang ◽  
Matt P. Page ◽  
Eugene Iwancizko ◽  
Yueqin Xu ◽  
Yanfa Yan ◽  
...  
Keyword(s):  
Solar Cells ◽  
Solar Cell ◽  
Amorphous Silicon ◽  
High Efficiency ◽  
Short Circuit ◽  
Open Circuit ◽  
Layer Growth ◽  
Surface Recombination Velocity ◽  
Back Contact ◽  
P Type

AbstractWe have achieved an independently-confirmed 17.8% conversion efficiency in a 1-cm2, p-type, float-zone silicon (FZ-Si) based heterojunction solar cell. Both the front emitter and back contact are hydrogenated amorphous silicon (a-Si:H) deposited by hot-wire chemical vapor deposition (HWCVD). This is the highest reported efficiency for a HWCVD silicon heterojunction (SHJ) solar cell. Two main improvements lead to our most recent increases in efficiency: 1) the use of textured Si wafers, and 2) the application of a-Si:H heterojunctions on both sides of the cell. Despite the use of textured c-Si to increase the short-circuit current, we were able to maintain the same 0.65 V open-circuit voltage as on flat c-Si. This is achieved by coating a-Si:H conformally on the c-Si surfaces, including covering the tips of the anisotropically-etched pyramids. A brief atomic H treatment before emitter deposition is not necessary on the textured wafers, though it was helpful in the flat wafers. It is essential to high efficiency SHJ solar cells that the emitter grows abruptly as amorphous silicon, instead of as microcrystalline or epitaxial Si. The contact on each side of the cell comprises a thin (< 5 nm) low substrate temperature (~100°C) intrinsic a-Si:H layer, followed by a doped layer. Our intrinsic layers are deposited at 0.3-1.2 nm/s. The doped emitter and back-contact layers were deposited at a higher temperature (>200°C) and grown from PH3/SiH4/H2 and B2H6/SiH4/H2 doping gas mixtures, respectively. This combination of low (intrinsic) and high (doped layer) growth temperatures was optimized by lifetime and surface recombination velocity measurements. Our rapid efficiency advance suggests that HWCVD may have advantages over plasma-enhanced (PE) CVD in fabrication of high-efficiency heterojunction c-Si cells; there is no need for process optimization to avoid plasma damage to the delicate, high-quality, Si wafers.

COMBINED EFFECT OF MECHANICAL GROOVING AND STAIN-ETCHED SURFACE ON OPTICAL AND ELECTRICAL PROPERTIES OF CRYSTALLINE SILICON SUBSTRATES

2014 ◽  
Vol 21 (03) ◽  
pp. 1450041 ◽  
Author(s):  
AHMED ZARROUG ◽  
LOTFI DERBALI ◽  
RACHID OUERTANI ◽  
WISSEM DIMASSI ◽  
HATEM EZZAOUIA
Keyword(s):  
Crystalline Silicon ◽  
Light Trapping ◽  
Front Surface ◽  
Minority Carrier Lifetime ◽  
Combined Effect ◽  
Machining Process ◽  
Silicon Substrates ◽  
Textured Surface ◽  
Crystalline Silicon Solar Cell ◽  
Simple Method

This paper investigates the combined effect of mechanical grooving and porous silicon (PS) on the front surface reflectance and the electronic properties of crystalline silicon substrates. Mechanical surface texturization leads to reduce the cell reflectance, enhance the light trapping and augment the carrier collection probability. PS was introduced as an efficient antireflective coating (ARC) onto the front surface of crystalline silicon solar cell. Micro-periodic V-shaped grooves were made by means of a micro-groove machining process prior to junction formation. Subsequently, wafers were subjected to an isotropic potassium hydroxide ( KOH ) etching so that the V-shape would be turned to a U-shape. We found that the successive treatment of silicon surfaces with stain-etching, grooving then alkaline etching enhances the absorption of the textured surface, and decreases the reflectance from 35% to 7% in the 300–1200 nm wavelength range. We obtained a significant increase in the overall light path that generates the building up of the light trapping inside the substrate. We found an improvement in the illuminated I–V characteristics and an increase in the minority carrier lifetime τeff. Such a simple method was adopted to effectively reinforce the overall device performance of crystalline silicon-based solar cells.

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