Improved electrical characteristics and reliability of multi-stacking PNPN junctionless transistors using channel depletion effect

2017 ◽  
Author(s):  
Ming-Huei Lin ◽  
Yi-Jia Shih ◽  
Chien Liu ◽  
Yu-Chien Chiu ◽  
Chia-Chi Fan ◽  
...  
Keyword(s):  
Electrical Characteristics ◽  
Depletion Effect ◽  
Junctionless Transistors

Effects of channel width variation on electrical characteristics of tri-gate Junctionless transistors

2013 ◽  
Vol 81 ◽  
pp. 58-62 ◽  
Author(s):  
Dae-Young Jeon ◽  
So Jeong Park ◽  
Mireille Mouis ◽  
Sylvain Barraud ◽  
Gyu-Tae Kim ◽  
...  
Keyword(s):  
Channel Width ◽  
Electrical Characteristics ◽  
Junctionless Transistors ◽  
Channel Width Variation

Effect of Channel Width Variation on Electrical Characteristics of Double Lateral Gate Junctionless Transistors; A Numerical Study

Silicon ◽  
2017 ◽  
Vol 10 (4) ◽  
pp. 1305-1314 ◽  
Author(s):  
Farhad Larki ◽  
Arash Dehzangi ◽  
Md. Shabiul Islam ◽  
Sawal Hamid Md Ali ◽  
Alam Abedini ◽  
...  
Keyword(s):  
Numerical Study ◽  
Channel Width ◽  
Electrical Characteristics ◽  
Junctionless Transistors ◽  
Lateral Gate ◽  
Channel Width Variation

scholarly journals Avaliação do desempenho do transistor MOS sem junções configurado como Nanofio ou FINFET

2020 ◽  
Author(s):  
◽  
T. A. Ribeiro
Keyword(s):  
Three Dimensional ◽  
Impurity Scattering ◽  
Coulomb Effect ◽  
Electrical Characteristics ◽  
Nanowire Transistors ◽  
Carrier Scattering ◽  
Effective Mobility ◽  
Junctionless Transistors ◽  
Transistor Mos ◽  
Long Channel

This work studies how the different gate configurations of junctionless transistors affects their electrical characteristics. Measurements were made on experimental junctionless transistors varying the fin width as well asthree-dimensional numerical simulations, which were calibrated with the experimental results, using the models that best apply to the physics of the junctionless devices. With the three-dimensional simulations adjusted for the fin width, a study was made based on the fin height and its electrical characteristics. These transistors can be configured either as FinFETs or as nanowires depending on the height of the silicon fin. It was obtained that junctionless FinFETs (fin height larger than the fin width), have their best electrical characteristics for long channel devices with narrow fin width and fin height with values greater than 30 nm. For junctionless nanowire transistors (similar fin height and fin width), the best potential can be seen with the decrease in the length of the channel, with narrow width and short height of the silicon fin (around 10 nm). The mobility of the experimental devices analyzed by the Split-CV method, obtaining the effective mobility of the transistors. It was obtained that for a decrease in the fin width it increases the mobility, due to the reduction of Ionized Impurity scattering. Measurements were also made due to the high temperature in triple gate junctionless nanowire transistors to almost planar devices in the range of 300 K to 500 K. It was analyzed by the effective mobility, the effects of the types of carrier scattering depending on the fin width experimentally and via simulations. It has been seen that quasi-planar transistors suffer less from the scattering effect by phonons compared to nanowires, the latter having a greater influence of surface roughness. Comparing the temperature exponents, junctionless transistors suffer more from the effect of scattering by phonons than with Coulomb effect in transistors with narrow fin width. Thus, narrow fin width devices have a greater variation of mobility with temperature compared to quasi-planar devices

scholarly journals Avaliação do desempenho do transistor MOS sem junções configurado como Nanofio ou FINFET

2020 ◽  
Author(s):  
◽  
T. A. Ribeiro
Keyword(s):  
Three Dimensional ◽  
Impurity Scattering ◽  
Coulomb Effect ◽  
Electrical Characteristics ◽  
Nanowire Transistors ◽  
Carrier Scattering ◽  
Effective Mobility ◽  
Junctionless Transistors ◽  
Transistor Mos ◽  
Long Channel

This work studies how the different gate configurations of junctionless transistors affects their electrical characteristics. Measurements were made on experimental junctionless transistors varying the fin width as well asthree-dimensional numerical simulations, which were calibrated with the experimental results, using the models that best apply to the physics of the junctionless devices. With the three-dimensional simulations adjusted for the fin width, a study was made based on the fin height and its electrical characteristics. These transistors can be configured either as FinFETs or as nanowires depending on the height of the silicon fin. It was obtained that junctionless FinFETs (fin height larger than the fin width), have their best electrical characteristics for long channel devices with narrow fin width and fin height with values greater than 30 nm. For junctionless nanowire transistors (similar fin height and fin width), the best potential can be seen with the decrease in the length of the channel, with narrow width and short height of the silicon fin (around 10 nm). The mobility of the experimental devices analyzed by the Split-CV method, obtaining the effective mobility of the transistors. It was obtained that for a decrease in the fin width it increases the mobility, due to the reduction of Ionized Impurity scattering. Measurements were also made due to the high temperature in triple gate junctionless nanowire transistors to almost planar devices in the range of 300 K to 500 K. It was analyzed by the effective mobility, the effects of the types of carrier scattering depending on the fin width experimentally and via simulations. It has been seen that quasi-planar transistors suffer less from the scattering effect by phonons compared to nanowires, the latter having a greater influence of surface roughness. Comparing the temperature exponents, junctionless transistors suffer more from the effect of scattering by phonons than with Coulomb effect in transistors with narrow fin width. Thus, narrow fin width devices have a greater variation of mobility with temperature compared to quasi-planar devices

The Electrical Characteristics of the MOSCAP Structures with W/WNx/poly Si1−XGeX Gates Stack

2001 ◽  
Vol 670 ◽  
Author(s):  
S.-K. Kang ◽  
J. J. Kim ◽  
D.-H. Ko ◽  
T. H. Ahn ◽  
I. S. Yeo ◽  
...  
Keyword(s):  
Leakage Current ◽  
Low Frequency ◽  
Current Level ◽  
Flat Band ◽  
Electrical Characteristics ◽  
Flat Band Voltage ◽  
Dopant Activation ◽  
Depletion Effect ◽  
Activation Rate ◽  
Boron Penetration

ABSTRACTWe investigated the electrical characteristics of the MOSCAP structures with W/WNx/poly Si1−xGex gates stack using C-V and I-V. The low frequency C-V measurements demonstrated that the flat band voltage of the W/WNx /poly Si0.4Ge0.6 stack was lower than that of W/ WNx /poly Si0.2Ge0.8 stack by 0.3V, and showed less gate-poly-depletion-effect than that of W/ WNx /poly- Si0.2Ge0.8 gates due to the increase of dopant activation rate with the increase of Ge content in the poly Si1−xGex films. As Ge content in poly Si1−xGex increased, the leakage current level increased a little due to the increase of direct tunneling and QBD became higher due to the lower boron penetration.

The Physical and Electrical Properties of Polycrystalline Si1−xGex as a Gate Electrode Material for ULSI CMOS Structures

2000 ◽  
Vol 611 ◽  
Author(s):  
Sung-Kwan Kang ◽  
Dae-Hong Ko ◽  
Tae-Hang Ahn ◽  
Moon-Sik Joo ◽  
In-Seok Yeo ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Flat Band ◽  
Electrical Characteristics ◽  
Flat Band Voltage ◽  
Gate Electrode ◽  
Promising Alternative ◽  
Depletion Effect ◽  
Si Films ◽  
Boron Penetration ◽  
Lower Resistivity

ABSTRACTPoly Si1−xGex films have been suggested as a promising alternative to the currently employed poly-Si gate electrode for CMOS technology due to lower resistivity, less boron penetration, and less gate depletion effect than those of poly Si gates. We investigated the formation of poly Si1−xGex films grown by UHV CVD using Si2H6 and GeH4 gases, and studied their microstructures as well as their electrical characteristics. The Ge content of the Si1−xGex films increased linearly with the flux of the GeH4 gas up to x=0.3, and saturated above x=0.45. The deposition rate of the poly Si1−xGex films increased linearly with the flux of the GeH4 gas up to x=0.1, above which it is slightly changed. The resistivity of the Si1−xGex films decreased as the Ge content increased, and was about one half of that of poly-Si films at the Ge content of 45%. The C-V measurements of the MOSCAP structures with poly Si1−xGex gates demonstrated that the flat band voltage of the poly Si1−xGex films was lower than that of poly-Si films by 0.2V.

In situ TEM measurements of the electrical properties of interface dislocations

1992 ◽  
Vol 50 (2) ◽  
pp. 1338-1339
Author(s):  
F. M. Ross ◽  
R. Hull ◽  
D. Bahnck ◽  
J. C. Bean ◽  
L. J. Peticolas ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Electronic Device ◽  
In Situ Tem ◽  
Device Performance ◽  
Misfit Dislocations ◽  
Electrical Characteristics ◽  
Strained Layer ◽  
Transmission Electron ◽  
Interfacial Dislocations

We describe an investigation of the electrical properties of interfacial dislocations in strained layer heterostructures. We have been measuring both the structural and electrical characteristics of strained layer p-n junction diodes simultaneously in a transmission electron microscope, enabling us to correlate changes in the electrical characteristics of a device with the formation of dislocations.The presence of dislocations within an electronic device is known to degrade the device performance. This degradation is of increasing significance in the design and processing of novel strained layer devices which may require layer thicknesses above the critical thickness (hc), where it is energetically favourable for the layers to relax by the formation of misfit dislocations at the strained interfaces. In order to quantify how device performance is affected when relaxation occurs we have therefore been investigating the electrical properties of dislocations at the p-n junction in Si/GeSi diodes.

The morphologies and electrical properties of indium contacts on (100) cadmium telluride surfaces

1992 ◽  
Vol 50 (2) ◽  
pp. 1422-1423
Author(s):  
A.M. Letsoalo ◽  
M.E. Lee ◽  
E.O. de Neijs
Keyword(s):  
Electrical Properties ◽  
Cadmium Telluride ◽  
Methanol Solution ◽  
Electrical Characteristics ◽  
Metal Contacts ◽  
Deposition Technique ◽  
Interfacial Layers ◽  
Semiconductor Contacts ◽  
Grown Single Crystal ◽  
Diamond Abrasive

Semiconductor devices require metal contacts for efficient collection of electrical charge. The physics of these metal/semiconductor contacts assumes perfect, abrupt and continuous interfaces between the layers. However, in practice these layers are neither continuous nor abrupt due to poor nucleation conditions and the formation of interfacial layers. The effects of layer thickness, deposition rate and substrate stoichiometry have been previously reported. In this work we will compare the effects of a single deposition technique and multiple depositions on the morphology of indium layers grown on (100) CdTe substrates. The electrical characteristics and specific resistivities of the indium contacts were measured, and their relationships with indium layer morphologies were established.Semi-insulating (100) CdTe samples were cut from Bridgman grown single crystal ingots. The surface of the as-cut slices were mechanically polished using 5μm, 3μm, 1μm and 0,25μm diamond abrasive respectively. This was followed by two minutes immersion in a 5% bromine-methanol solution.

P.3.6 Acute and chronic electrical characteristics of atrial leads: A data registry

EP Europace ◽  
2003 ◽  
Vol 4 ◽  
pp. A47
Author(s):  
P PEYTCHEV
Keyword(s):  
Electrical Characteristics ◽  
Data Registry
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