Application of Laser Treatment in MOS-TFT Active Layer Prepared by Solution Method

The active layer of metal oxide semiconductor thin film transistor (MOS-TFT) prepared by solution method, with the advantages of being a low cost and simple preparation process, usually needs heat treatment to improve its performance. Laser treatment has the advantages of high energy, fast speed, less damage to the substrate and controllable treatment area, which is more suitable for flexible and large-scale roll-to-roll preparation than thermal treatment. This paper mainly introduces the basic principle of active layer thin films prepared by laser treatment solution, including laser photochemical cracking of metastable bonds, laser thermal effect, photoactivation effect and laser sintering of nanoparticles. In addition, the application of laser treatment in the regulation of MOS-TFT performance is also described, including the effects of laser energy density, treatment atmosphere, laser wavelength and other factors on the performance of active layer thin films and MOS-TFT devices. Finally, the problems and future development trends of laser treatment technology in the application of metal oxide semiconductor thin films prepared by solution method and MOS-TFT are summarized.

Exploration of Ion Sensitive Field-Effect Transistor With Dielectric Properties

Environmental changes and increased virus effects in COVID-19 like the situation is forcing the design and researchers to develop highly sensitive, low power and low cost mean to detect the presence of biomolecules of different shapes, sizes, and their effects on the human being. Ion-sensitive field-effect transistor (IS-FET) is a biological sensor based on the architecture of metal oxide semiconductor field-effect transistor (MOS-FET). The gate terminal is replaced with a hollow space filled by electrolyte solution and reference electrode at the external surface. The biomolecular enzyme in contact with membrane enters in solution induce net DC potential, alter the oxide surface. The alteration of surface puts variation in threshold voltage and maps on the deflection of drain current. ISFET measures the concentration of charged particles (ions) in the solution; variation into ion concentration produces deflection in the drain current. In this work numerical simulation of ISFET is performed with ENBIOS-2D Lab at Nanohub platform with dielectric SiO2, Al2O3, HfO2 with NaCl and KCl in solution. Channel resistance and capacitance with 3-different electric shows a large variation of capacitance, result in threshold voltage i.e. 318.2 mV with SiO2 and 319.2 mV with Al2O3.

Performance Enhancement in N2 Plasma Modified AlGaN/AlN/GaN MOS-HEMT Using HfAlOX Gate Dielectric with Γ-Shaped Gate Engineering

In this paper, we have demonstrated the optimized device performance in the Γ-shaped gate AlGaN/AlN/GaN metal oxide semiconductor high electron mobility transistor (MOS-HEMT) by incorporating aluminum into atomic layer deposited (ALD) HfO2 and comparing it with the commonly used HfO2 gate dielectric with the N2 surface plasma treatment. The inclusion of Al in the HfO2 increased the crystalline temperature (~1000 °C) of hafnium aluminate (HfAlOX) and kept the material in the amorphous stage even at very high annealing temperature (>800 °C), which subsequently improved the device performance. The gate leakage current (IG) was significantly reduced with the increasing post deposition annealing (PDA) temperature from 300 to 600 °C in HfAlOX-based MOS-HEMT, compared to the HfO2-based device. In comparison with HfO2 gate dielectric, the interface state density (Dit) can be reduced significantly using HfAlOX due to the effective passivation of the dangling bond. The greater band offset of the HfAlOX than HfO2 reduces the tunneling current through the gate dielectric at room temperature (RT), which resulted in the lower IG in Γ-gate HfAlOX MOS-HEMT. Moreover, IG was reduced more than one order of magnitude in HfAlOX MOS-HEMT by the N2 surface plasma treatment, due to reduction of N2 vacancies which were created by ICP dry etching. The N2 plasma treated Γ-shaped gate HfAlOX-based MOS-HEMT exhibited a decent performance with IDMAX of 870 mA/mm, GMMAX of 118 mS/mm, threshold voltage (VTH) of −3.55 V, higher ION/IOFF ratio of approximately 1.8 × 109, subthreshold slope (SS) of 90 mV/dec, and a high VBR of 195 V with reduced gate leakage current of 1.3 × 10−10 A/mm.

Study of Effective Graded Oxide Capacitance and Length Variation on Analog, RF and Power Performances of Dual Gate Underlap MOS-HEMT

Comparative analysis of a Symmetric Heterojunction Underlap Double Gate (U-DG) GaN/AlGaN Metal Oxide Semiconductor High Electron Mobility Transistor (MOS-HEMT) on varying the effective capacitance by using different oxide materials on source and drain sides, and determination of optimum length of oxides for the superior device performance has been presented in this work. This paper shows a detailed performance analysis of the Analog Figure of Merits (FoMs) like variation of Drain Current (IDS), Transconductance (gm), Output Resistance (R0), Intrinsic Gain (gmR0), RF FoMs like cut-off frequency (fT), maximum frequency of oscillation (fMAX), gate to source resistance (RGS), gate to drain resistance (RGD), gate to drain capacitance(CGD), gate to source capacitance (CGS) and total gate capacitance (CGG) using Non-Quasi-Static (NQS) approach. Power analysis includes Output power (Pout), Gain in dBm and power output efficiency (POE) have been studied. Studies reveal that the device with higher dielectric material towards source side shows superior performance. On subsequently changing the proportion of two oxides in a layer by varying length, it is observed that as the proportion of oxide increases the device demonstrates more desirable Analog and RF characteristics while best power performance is obtained from device with equal lengths of HfO2 and SiO2.

Inverted-Type InAlAs/InAs High-Electron-Mobility Transistor with Liquid Phase Oxidized InAlAs as Gate Insulator

An inverted-type InAlAs/InAs metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT) with liquid phase oxidized (LPO) InAlAs as the gate insulator is demonstrated. A thin InAs layer is inserted in the sub-channel layers of InGaAs to enhance the device performance. The proposed inverted-type InAlAs/InAs MOS-HEMT exhibits an improved maximum drain current density, higher transconductance, lower leakage current density, suppressed noise figures, and enhanced associated gain compared to the conventional Schottky-gate HEMT. Employing LPO to generate MOS structure improves the surface states and enhances the energy barrier. These results reveal that the proposed inverted-type InAlAs/InAs MOS-HEMT can provide an alternative option for device applications.

Comparative Investigation of AlGaN/AlN/GaN High Electron Mobility Transistors with Pd/GaN and Pd/Al2O3/GaN Gate Structures

In this article, the electrical characteristics of Al0.28Ga0.72 N/AlN/GaN metal-oxide-semiconductor high electron mobility transistor (MOS-HEMT) with a 20-nm-thick Al2O3 layer by using radio-frequency sputtering as the gate dielectric layer are compared to the conventional metal-semiconductor HEMT (MS-HEMT) with Pd/GaN gate structure. For the insertion of the Al2O3 layer, the energy band near the AlN/GaN heterojunction is lifted slightly up and the 2DEG at the heterojunction is reduced to shift the threshold voltage to the right side. Experimental results exhibits that though the maximum drain current decreases about 6.5%, the maximum transconductance increases of 9%, and the gate leakage current significantly reduces about five orders of magnitude for the MOS-HEMT than the MS-HEMT.

New Insight on Terahertz Rectification in a Metal–Oxide–Semiconductor Field-Effect Transistor Structure

The use of a metal–oxide–semiconductor field-effect transistor (MOS-FET) permits the rectification of electromagnetic radiation by employing integrated circuit technology. However, obtaining a high-efficiency rectification device requires the assessment of a physical model capable of providing a qualitative and quantitative explanation of the processes involved. For a long time, high-frequency detection based on MOS technology was explained using plasma wave detection theory. In this paper, we review the rectification mechanism in light of high-frequency numerical simulations, showing features never examined until now. The results achieved substantially change our understanding of terahertz (THz) rectification in semiconductors, and can be interpreted by the model based on the self-mixing process in the device substrate, providing a new and essential tool for designing this type of detector.

Avaliação do desempenho do transistor MOS sem junções configurado como Nanofio ou FINFET

This work studies how the different gate configurations of junctionless transistors affects their electrical characteristics. Measurements were made on experimental junctionless transistors varying the fin width as well asthree-dimensional numerical simulations, which were calibrated with the experimental results, using the models that best apply to the physics of the junctionless devices. With the three-dimensional simulations adjusted for the fin width, a study was made based on the fin height and its electrical characteristics. These transistors can be configured either as FinFETs or as nanowires depending on the height of the silicon fin. It was obtained that junctionless FinFETs (fin height larger than the fin width), have their best electrical characteristics for long channel devices with narrow fin width and fin height with values greater than 30 nm. For junctionless nanowire transistors (similar fin height and fin width), the best potential can be seen with the decrease in the length of the channel, with narrow width and short height of the silicon fin (around 10 nm). The mobility of the experimental devices analyzed by the Split-CV method, obtaining the effective mobility of the transistors. It was obtained that for a decrease in the fin width it increases the mobility, due to the reduction of Ionized Impurity scattering. Measurements were also made due to the high temperature in triple gate junctionless nanowire transistors to almost planar devices in the range of 300 K to 500 K. It was analyzed by the effective mobility, the effects of the types of carrier scattering depending on the fin width experimentally and via simulations. It has been seen that quasi-planar transistors suffer less from the scattering effect by phonons compared to nanowires, the latter having a greater influence of surface roughness. Comparing the temperature exponents, junctionless transistors suffer more from the effect of scattering by phonons than with Coulomb effect in transistors with narrow fin width. Thus, narrow fin width devices have a greater variation of mobility with temperature compared to quasi-planar devices

Avaliação do desempenho do transistor MOS sem junções configurado como Nanofio ou FINFET

This work studies how the different gate configurations of junctionless transistors affects their electrical characteristics. Measurements were made on experimental junctionless transistors varying the fin width as well asthree-dimensional numerical simulations, which were calibrated with the experimental results, using the models that best apply to the physics of the junctionless devices. With the three-dimensional simulations adjusted for the fin width, a study was made based on the fin height and its electrical characteristics. These transistors can be configured either as FinFETs or as nanowires depending on the height of the silicon fin. It was obtained that junctionless FinFETs (fin height larger than the fin width), have their best electrical characteristics for long channel devices with narrow fin width and fin height with values greater than 30 nm. For junctionless nanowire transistors (similar fin height and fin width), the best potential can be seen with the decrease in the length of the channel, with narrow width and short height of the silicon fin (around 10 nm). The mobility of the experimental devices analyzed by the Split-CV method, obtaining the effective mobility of the transistors. It was obtained that for a decrease in the fin width it increases the mobility, due to the reduction of Ionized Impurity scattering. Measurements were also made due to the high temperature in triple gate junctionless nanowire transistors to almost planar devices in the range of 300 K to 500 K. It was analyzed by the effective mobility, the effects of the types of carrier scattering depending on the fin width experimentally and via simulations. It has been seen that quasi-planar transistors suffer less from the scattering effect by phonons compared to nanowires, the latter having a greater influence of surface roughness. Comparing the temperature exponents, junctionless transistors suffer more from the effect of scattering by phonons than with Coulomb effect in transistors with narrow fin width. Thus, narrow fin width devices have a greater variation of mobility with temperature compared to quasi-planar devices

Spatial Wavefunction Switched (SWS) FET SRAM Circuits and Simulation

This paper presents the design and simulation of static random access memory (SRAM) using two channel spatial wavefunction switched field-effect transistor (SWS-FET), also known as a twin-drain metal oxide semiconductor field effect transistor (MOS-FET). In the SWS-FET, the channel between source and drain has two quantum well layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the quantum well layers and it causes the switching of charge carriers from one channel to other channel of the device. The standard SRAM circuit has six transistors (6T), two p-type MOS-FET and four n-type MOS-FET. By using the SWSFET, the size and the number of transistors are reduced and all of transistors are n-channel SWS-FET. This paper proposes two different models of the SWS-FET SRAM circuits with three transistors (3T) and four transistors (4T) also addresses the stability of the proposed SWS-FET SRAM circuits by using the N-curve analysis. The proposed models are based on integration between Berkeley Shortchannel IGFET Model (BSIM) and Analog Behavioral Model (ABM), the model is suitable to investigate the gates configuration and transient analysis at circuit level.