scholarly journals S-curve Engineering for ON-state Performance using Anti-ferroelectric/Ferroelectric Stack Negative-Capacitance FinFET

2021 ◽  
Author(s):  
Shih-En Huang ◽  
Pin Su ◽  
Chenming Hu
Keyword(s):  
Series Resistance ◽  
Single Layer ◽  
Negative Capacitance ◽  
Gate Bias ◽  
Gate Stack ◽  
Short Channel ◽  
Ic Manufacturing ◽  
Strong Inversion ◽  
S Curve

<div>In this work, we report that the AFE/FE gate-stack can be utilized to engineer the S-curve for boosting the I<sub>ON</sub> of NC-FinFET. By using a short-channel BSIM-CMG compatible AFE/FE stack NC-FinFET model, the capacitance matching and ON-state performance for AFE/FE stack NC-FinFETs are investigated. Our study indicates that, the AFE/FE gate-stack can be used to improve the capacitance matching in strong inversion at higher gate-bias. Therefore, impressively higher ON-state current (compared to single-layer) can be achieved. In reality, source-drain series resistance will make such high IDS impractical. The more likely strategy is to use lower V<sub>DD</sub> to achieve much lower power consumption (and reduced vertical fields). While the transient NC effect also needs to be carefully investigated, this study suggests significant long term benefits to V<sub>DD</sub> scaling if materials with certain AFE and FE properties are developed and introduced in IC manufacturing in the future.</div>

scholarly journals S-curve Engineering for ON-state Performance using Anti-ferroelectric/Ferroelectric Stack Negative-Capacitance FinFET

2021 ◽  
Author(s):  
Shih-En Huang ◽  
Pin Su ◽  
Chenming Hu
Keyword(s):  
Series Resistance ◽  
Single Layer ◽  
Negative Capacitance ◽  
Gate Bias ◽  
Gate Stack ◽  
Short Channel ◽  
Ic Manufacturing ◽  
Strong Inversion ◽  
S Curve

<div>In this work, we report that the AFE/FE gate-stack can be utilized to engineer the S-curve for boosting the I<sub>ON</sub> of NC-FinFET. By using a short-channel BSIM-CMG compatible AFE/FE stack NC-FinFET model, the capacitance matching and ON-state performance for AFE/FE stack NC-FinFETs are investigated. Our study indicates that, the AFE/FE gate-stack can be used to improve the capacitance matching in strong inversion at higher gate-bias. Therefore, impressively higher ON-state current (compared to single-layer) can be achieved. In reality, source-drain series resistance will make such high IDS impractical. The more likely strategy is to use lower V<sub>DD</sub> to achieve much lower power consumption (and reduced vertical fields). While the transient NC effect also needs to be carefully investigated, this study suggests significant long term benefits to V<sub>DD</sub> scaling if materials with certain AFE and FE properties are developed and introduced in IC manufacturing in the future.</div>

scholarly journals Extraction of Series Resistance and Mobility Degradation in MOSFETs Using Iterative Method

2020 ◽  
Vol 5 (1) ◽  
pp. 21-27
Author(s):  
Noureddine Maouhoub ◽  
Khalid Rais
Keyword(s):  
Iterative Method ◽  
Series Resistance ◽  
Exponential Model ◽  
Short Channel ◽  
Attenuation Parameter ◽  
Low Field ◽  
Mobility Degradation ◽  
Strong Inversion ◽  
Roughness Amplitude ◽  
Good Agreement

Series resistance and mobility attenuation parameter are parasitic phenomena that limit the scaling of advanced MOSFETs. In this work, an iterative method is proposed to extract the series resistance and mobility degradation parameter in short channel MOSFETs. It also allows us to extract the surface roughness amplitude. The principle of this method is based on the exponential model of effective mobility and the least squares methods. From these, two analytical equations are obtained to determine the series resistance and the low field mobility as function of the mobility degradation. The mobility attenuation parameter is extracted using an iterative procedure to minimize the root means squared error (RMSE) value. The results obtained by this technique for a single short channel device have shown the good agreement with measurements data at strong inversion.  

scholarly journals Extraction of series resistance and mobility degradation parameter in MOSFETs using iterative method

2020 ◽  
Vol 1 (1) ◽  
pp. 26-31
Author(s):  
Noureddine Maouhoub ◽  
Khalid Rais
Keyword(s):  
Iterative Method ◽  
Series Resistance ◽  
Exponential Model ◽  
Short Channel ◽  
Attenuation Parameter ◽  
Low Field ◽  
Mobility Degradation ◽  
Strong Inversion ◽  
Roughness Amplitude ◽  
Good Agreement

Series resistance and mobility attenuation parameter are parasitic phenomena that limit the scaling of advanced MOSFETs. In this work, an iterative method is proposed to extract the series resistance and mobility degradation parameter in short channel MOSFETs. It also allows us to extract the surface roughness amplitude. The principle of this method is based on the exponential model of effective mobility and the least squares methods. From these, two analytical equations are obtained to determine the series resistance and the low field mobility as function of the mobility degradation. The mobility attenuation parameter is extracted using an iterative procedure to minimize the root means squared error (RMSE) value. The results obtained by this technique for a single short channel device have shown the good agreement with measurements data at strong inversion. 

scholarly journals Characterization of Series Resistance and Mobility Degradation Parameter and Optimizing Choice of Oxide Thickness in Thin OxideN-Channel MOSFET

2011 ◽  
Vol 2011 ◽  
pp. 1-4 ◽  
Author(s):  
Noureddine Maouhoub ◽  
Khalid Rais
Keyword(s):  
Series Resistance ◽  
Classical Model ◽  
Drain Current ◽  
Oxide Thickness ◽  
Exponential Model ◽  
Short Channel ◽  
Mobility Degradation ◽  
Strong Inversion ◽  
Roughness Amplitude ◽  
Two Parameters

We present two methods to extract the series resistance and the mobility degradation parameter in short-channel MOSFETs. The principle of the first method is based on the comparison between the exponential model and the classical model of effective mobility and for the second method is based on directly calculating the two parameters by solving a system of two equations obtained by using two different points in strong inversion at small drain bias from the characteristic (). The results obtained by these techniques have shown a better agreement with data measurements and allowed in the same time to determine the surface roughness amplitude and its influence on the maximum drain current and give the optimal oxide thickness.

Short-channel robustness from negative capacitance in 2D NC-FETs

2021 ◽  
Vol 118 (10) ◽  
pp. 101903
Author(s):  
Yuh-Chen Lin ◽  
G. Bruce Rayner ◽  
Jorge Cardenas ◽  
Aaron D. Franklin
Keyword(s):  
Negative Capacitance ◽  
Short Channel

scholarly journals Atomic Layer Deposition (ALD) of Metal Gates for CMOS

2019 ◽  
Vol 9 (11) ◽  
pp. 2388 ◽  
Author(s):  
Chao Zhao ◽  
Jinjuan Xiang
Keyword(s):  
Atomic Layer Deposition ◽  
Field Effect Transistors ◽  
Material Selection ◽  
Atomic Layer ◽  
Oxide Semiconductor ◽  
Metal Gate ◽  
Gate Stack ◽  
Short Channel ◽  
Metal Gates ◽  
Layer Deposition

The continuous down-scaling of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) had been suffering two fateful technical issues, one relative to the thinning of gate dielectric and the other to the aggressive shortening of channel in last 20 years. To solve the first issue, the high-κ dielectric and metal gate technology had been induced to replace the conventional gate stack of silicon dioxide layer and poly-silicon. To suppress the short channel effects, device architecture had changed from planar bulk Si device to fully depleted silicon on insulator (FDSOI) and FinFETs, and will transit to gate all-around FETs (GAA-FETs). Different from the planar devices, the FinFETs and GAA-FETs have a 3D channel. The conventional high-κ/metal gate process using sputtering faces conformality difficulty, and all atomic layer deposition (ALD) of gate stack become necessary. This review covers both scientific and technological parts related to the ALD of metal gates including the concept of effect work function, the material selection, the precursors for the deposition, the threshold voltage (Vt) tuning of the metal gate in contact with HfO2/SiO2/Si. The ALD of n-type metal gate will be detailed systematically, based mainly on the authors’ works in last five years, and the all ALD gate stacks will be proposed for the future generations based on the learning.

scholarly journals Novel Negative Capacitance and Conductance in All Temperatures and Voltages of Au/CNTs/n-Si/Al at Low and High Frequencies

2021 ◽  
Author(s):  
A. Ashery ◽  
Samia Gad ◽  
A. E.H. Gaballah ◽  
G. M. Turky
Keyword(s):  
Carbon Nanotube ◽  
High Frequency ◽  
Series Resistance ◽  
Negative Capacitance ◽  
Donor Concentration ◽  
Low Frequencies ◽  
High Frequencies ◽  
Depletion Width ◽  
Density Surface ◽  
P Type

Abstract The structure of carbon nanotube CNTs functioning as p-type material deposited over n-type silicon to produce heterojunction of Au/CNTs/n-Si/Al is presented in this study.This work explored the capacitance and conductance at various frequencies, temperatures, and voltages, the novelty here is that negative capacitance and conductance were observed at high frequencies in all temperatures and voltages, whereas capacitance appeared at both high and low frequencies, such as (2x107,1x107,1x102,10) Hz. At high-frequency f = 2x107 Hz, the capacitance raises while the conductance decreases; at all temperatures and voltages, the capacitance and conductance exhibit the same behavior at particular frequencies such as 1x106,1x105,1x104,1x103Hz, however their behavior differs at 2x107,1x107, 1x102 and 10Hz. Investigating the reverse square capacitance with voltage yielded the energy fermi (Ef), density surface of states (Nss), depletion width (Wd), barrier height, series resistance, and donor concentration (Nd)

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