scholarly journals A Novel Approach to Design 2-bit Binary Arithmetic Logic Unit (ALU) Circuit Using Optimized 8:1 Multiplexer with Reversible logic

2015 ◽  
Vol 11 (2) ◽  
pp. 104
Author(s):  
Vandana Shukla ◽  
O. P. Singh ◽  
G. R. Mishra ◽  
R. K. Tiwari
Keyword(s):  
Low Power ◽  
Optical Computing ◽  
Reversible Logic ◽  
Low Loss ◽  
Arithmetic Logic Unit ◽  
Novel Approach ◽  
Cmos Design ◽  
Binary Arithmetic ◽  
Low Power Cmos ◽  
Logic Unit

Reversible circuit designing is the area where researchers are focussing more and more for the generation of low loss digital system designs. Researchers are using the concept of Reversible Logic in many areas such as Nanotechnology, low loss computing, optical computing, low power CMOS design etc. Here we have proposed a novel design approach for a 2-bit binary Arithmetic Logic Unit (ALU) using optimized 8:1 multiplexer circuit with reversible logic concept [1]. This ALU circuit can perform complement, transfer, addition, subtraction, multiplication, OR, XOR, NAND functions on given values. The ALU circuit has been simulated on Modelsim tool and synthesised for Xilinx Spartan 3E with Device XC3S500E with 200 MHz frequency. This 2-bit ALU using reversible logic is useful for the designs of low power loss systems.

Design and Implementation of Four Bit Binary Shifter Circuit Using Reversible Logic Approach

2015 ◽  
Vol 4 (3) ◽  
pp. 213
Author(s):  
Vandana Shukla ◽  
O. P. Singh ◽  
G. R. Mishra ◽  
R. K. Tiwari
Keyword(s):  
Low Power ◽  
Optical Computing ◽  
Logic Gates ◽  
Reversible Logic ◽  
Optimized Design ◽  
Storage Unit ◽  
Computing Device ◽  
Cmos Design ◽  
Low Power Cmos ◽  
Logic Approach

Shifter circuits are the key component of arithmetic logic unit as well as storage unit of any digital computing device. Designing these shifter circuits using reversible logic approach leads to create low power loss digital systems. Reversible circuit design approach is nowadays widely applicable in various disciplines such as Nanotechnology, Low power CMOS design, Optical computing etc. This paper presents two design approaches for four bit binary combinational shifter circuit with the help of different types of reversible logic gates. The proposed optimized design is simulated using Modelsim tool and synthesised for Xilinx Spartan 3E with Device XC3S500E with 200 MHz frequency.

scholarly journals A Novel Design and Evaluation of a Low Power Efficient Fault-Tolerant Reversible ALU Using QCA: Applications of Nanoelectronics

2021 ◽  
Author(s):  
Mary Swarna Latha Gade ◽  
Rooban S
Keyword(s):  
Low Power ◽  
High Speed ◽  
Fault Tolerant ◽  
Logic Gates ◽  
Reversible Logic ◽  
Functional Verification ◽  
Logical Operations ◽  
Arithmetic Logic Unit ◽  
Reversible Alu ◽  
Logic Unit

Abstract Reversible logic based on Quantum-dot Cellular Automata (QCA) is the most requirement for achieving nano-scale architecture that promises significantly high device integration density, high-speed calculation, and low power consumption. The arithmetic logic unit (ALU) is the significant component of a processor for processing and computing. The primary objective of this work is to develop a multi-layer fault-tolerant arithmetic logic unit using reversible logic in QCA technology. Additionally, the reversible ALU has divided into arithmetic (RAU) and a logic unit (RLU). A reversible 2:1 MUX using the Fredkin gate has been implemented to select either the arithmetic or logical operations. Besides, to improve the efficiency of arithmetic operations, a novel QCA reversible full adder is implemented. To build the ALU, fault-tolerant reversible logic gates are used. The proposed reversible multilayer QCA ALU is designed to carry out eight arithmetic and sixteen logical operations with a minimum number of gates, constant inputs, and garbage outputs compared to the existing works. The functional verification and simulation of the presented circuits are assessed by the QCADesigner tool.

scholarly journals Reversible logic in pipelined low power vedic multiplier

2019 ◽  
Vol 16 (3) ◽  
pp. 1265
Author(s):  
Ansiya Eshack ◽  
S. Krishnakumar
Keyword(s):  
Low Power ◽  
Communication Systems ◽  
Large Scale ◽  
Optical Computing ◽  
Digital Signal ◽  
Logic Gates ◽  
Reversible Logic ◽  
Large Scale Integration ◽  
Time Required ◽  
Scale Integration

<span>With an ever growing demand for low-power devices, it is a general trend to search for ways to reduce the power consumption of a system. Multipliers are an important requirement in applications linked to Digital Signal Processing, Communication Systems, Optical Computing, Nanotechnology, Low-Power Very Large Scale Integration and Quantum Computing. Conventional mathematics makes multiplication a very long and time consuming process. The use of Vedic mathematics has led to great reduction in the time required for such calculations. The excessive use of Urdhava Tiryakbhyam sutra in multiplication surely proves its effectiveness and simplicity in this domain. This sutra supports the process of pipelining, a method employed in reduction of the power used by a system. Reversible logic has been gaining demand due to its low-power capabilities and is currently being used in many computing applications. The paper proposes two multiplier systems: one design employs the Urdhava Tiryakbhyam sutra along with pipelining and the second uses reversible logic gates into the first design. These proposed systems provide very less delay for result computation and low hardware utilization when compared to non-pipelined Vedic multipliers.</span>

Design of Combinational Circuits Using Reversible Decoder in Tanner Tools

2020 ◽  
Vol 17 (4) ◽  
pp. 1743-1751
Author(s):  
R. Kannan ◽  
K. Vidhya
Keyword(s):  
Low Power ◽  
Optical Computing ◽  
Logic Gates ◽  
Full Adder ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Combinational Circuits ◽  
Nano Technology ◽  
Feynman Gate ◽  
Reversible Logic Gates

Reversible logic is the emerging field for research in present era. The aim of this paper is to realize different types of combinational circuits like full-adder, full-subtractor, multiplexer and comparator using reversible decoder circuit with minimum quantum cost. Reversible decoder is designed using Fredkin gates with minimum Quantum cost. There are many reversible logic gates like Fredkin Gate, Feynman Gate, Double Feynman Gate, Peres Gate, Seynman Gate and many more. Reversible logic is defined as the logic in which the number output lines are equal to the number of input lines i.e., the n-input and k-output Boolean function F(X1,X2,X3, ...,Xn) (referred to as (n,k) function) is said to be reversible if and only if (i) n is equal to k and (ii) each input pattern is mapped uniquely to output pattern. The gate must run forward and backward that is the inputs can also be retrieved from outputs. When the device obeys these two conditions then the second law of thermo-dynamics guarantees that it dissipates no heat. Fan-out and Feed-back are not allowed in Logical Reversibility. Reversible Logic owns its applications in various fields which include Quantum Computing, Optical Computing, Nano-technology, Computer Graphics, low power VLSI etc. Reversible logic is gaining its own importance in recent years largely due to its property of low power consumption. The comparative study in terms of garbage outputs, Quantum Cost, numbers of gates are also presented. The Circuit has been implemented and simulated using Tannaer tools v15.0 software.

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