scholarly journals The Research on the structure and configuration of MCU clock system for Kinets series

Author(s):  
Jing Wang ◽  
Zhenchong Wang
Keyword(s):  
GPS Solutions ◽  
2021 ◽  
Vol 25 (3) ◽  
Author(s):  
Damon Van Buren ◽  
Penina Axelrad ◽  
Scott Palo

AbstractWe describe our investigation into the performance of low-power heterogeneous timing systems for small satellites, using real GPS observables from the GRACE Follow-On mission. Small satellites have become capable platforms for a wide range of commercial, scientific and defense missions, but they are still unable to meet the needs of missions that require precise timing, on the order of a few nanoseconds. Improved low-power onboard clocks would make small satellites a viable option for even more missions, enabling radio aperture interferometry, improved radio occultation measurements, high altitude GPS navigation, and GPS augmentation missions, among others. One approach for providing improved small satellite timekeeping is to combine a heterogeneous group of oscillators, each of which provides the best stability over a different time frame. A hardware architecture that uses a single-crystal oscillator, one or more Chip Scale Atomic Clocks (CSACs) and the reference time from a GPS receiver is presented. The clocks each contribute stability over a subset of timeframes, resulting in excellent overall system stability for timeframes ranging from less than a second to several days. A Kalman filter is used to estimate the long-term errors of the CSACs based on the CSAC-GPS time difference, and the improved CSAC time is used to discipline the crystal oscillator, which provides the high-stability reference clock for the small satellite. Simulations using GRACE-FO observations show time error standard deviations for the system range from 2.3 ns down to 1.3 ns for the clock system, depending on how many CSACs are used. The results provide insight into the timing performance which could be achieved on small LEO spacecraft by a low power timing system.


2011 ◽  
Vol 187 ◽  
pp. 741-745 ◽  
Author(s):  
Juan Hua Zhu ◽  
Ang Wu ◽  
Juan Fang Zhu

A digital clock system designed by using VHDL hardware description language is presented in this paper. The proposed architecture fully utilizes the digital clock system available on FPGA chips based top-down design method in the Quartus II development environment. The Clock system is divided into four design modules: core module, frequency_division module, display module and tune module. It not only can time accurately and display time, but also can reset and adjust time. The LED lights will flash and the loudspeaker will tell time on the hour. The architecture is implemented and verified experimentally on a FPGA board. Because of the universality of digital clock and the portability of VHDL language, it can be applied directly in various designs based on FPGA chip.


2018 ◽  
Vol 14 (7) ◽  
pp. 791-798 ◽  
Author(s):  
Suliman Khan ◽  
Ghulam Nabi ◽  
Lunguang Yao ◽  
Rabeea Siddique ◽  
Wasim Sajjad ◽  
...  

2016 ◽  
Vol 74 (4) ◽  
pp. 299-302 ◽  
Author(s):  
Vanessa Fernanda Moreira Ferreira ◽  
Gabriel Pina Paiva ◽  
Natália Prando ◽  
Carla Renata Graça ◽  
João Aris Kouyoumdjian

ABSTRACT Our internal clock system is predominantly dopaminergic, but memory is predominantly cholinergic. Here, we examined the common sensibility encapsulated in the statement: “time goes faster as we get older”. Objective To measure a 2 min time interval, counted mentally in subjects of different age groups. Method 233 healthy subjects (129 women) were divided into three age groups: G1, 15-29 years; G2, 30-49 years; and G3, 50-89 years. Subjects were asked to close their eyes and mentally count the passing of 120 s. Results The elapsed times were: G1, mean = 114.9 ± 35 s; G2, mean = 96.0 ± 34.3 s; G3, mean = 86.6 ± 34.9 s. The ANOVA-Bonferroni multiple comparison test showed that G3 and G1 results were significantly different (P < 0.001). Conclusion Mental calculations of 120 s were shortened by an average of 24.6% (28.3 s) in individuals over age 50 years compared to individuals under age 30 years.


2021 ◽  
Author(s):  
Gunnar Carlstedt ◽  
Mats Rimborg

<div>A clock system for a huge grid of small clock regions is presented. There is an oscillator in each clock region, which drives the local clock of a processing element (PE). The oscillators are kept synchronized by exploiting the phase of their neighbors. In an infinite mesh, the clock skew would be zero, but in a network of limited size there will be fringe effects. In a mesh with 25×25 oscillators, the maximum skew between neighboring regions is within 3.3 ps. By slightly adjusting the free running frequency of the oscillators, this skew can be reduced to 1.2 ps. The mesh may contain millions of clock regions.</div><div> Because there is no central clock, both power consumption and clock frequency can be improved compared to a conventional clock distribution network. A PE of 150×150 µm² running at 6.7 GHz with 93 master-slave flip-flops is used as an example. The PE-internal clock skew is less than 2.3 ps, and the energy consumption of the clock system 807 µW per PE. It corresponds to an effective gate and wire capacitance of 509 aF, or 7.3 gate capacitances.</div><div> Power noise is reduced by scheduling the local oscillators gradually along one of the grid’s axes. In this way, surge currents, which generally have their peaks at the clock edges, are distributed evenly over a full clock cycle.</div>


2019 ◽  
Vol 3 (Supplement_1) ◽  
Author(s):  
Vinicius Soares ◽  
Clarissa Martins ◽  
Edson Martinez ◽  
Leonardo Domingues de Araújo ◽  
Silvia Roa ◽  
...  

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