scholarly journals Uniform Quantization of Signals with Clipped and Truncated Laplace Distributions

2020 ◽  
Author(s):  
Jerald Bauck
Keyword(s):  
Signal To Noise Ratio ◽  
Laplace Distribution ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Signal To Noise ◽  
Analog To Digital ◽  
Traditional Test ◽  
Uniform Quantization ◽  
Long Tails ◽  
Noise Ratio

Many natural and man-made signals including much of speech and music are well-modeled by the Laplace distribution. Methods of synthesizing such signals are available and sometimes preferred over traditional test signals. However, sometimes those Laplace-like signals are clipped or do not exhibit infinitely-long tails. These situations are analyzed to determine their variances with an application of estimating signal-to-noise ratio as they are quantized by an analog-to-digital converter.

scholarly journals Modeling of High-Resolution Data Converter: Two-Step Pipelined-SAR ADC based on ISDM

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 137 ◽  
Author(s):  
Bo Gao ◽  
Xin Li ◽  
Jie Sun ◽  
Jianhui Wu
Keyword(s):  
High Resolution ◽  
Low Noise ◽  
Sar Adc ◽  
Total Power ◽  
Cmos Process ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Signal To Noise ◽  
Analog To Digital ◽  
High Bandwidth

The features of high-resolution and high-bandwidth are in an increasing demand considering to the wide range application fields based on high performance data converters. In this paper, a modeling of high-resolution hybrid analog-to-digital converter (ADC) is proposed to meet those requirements, and a 16-bit two-step pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with first-order continuous-time incremental sigma-delta modulator (ISDM) assisted is presented to verify this modeling. The combination of high-bandwidth two-step pipelined-SAR ADC with low noise ISDM and background comparator offset calibration can achieve higher signal-to-noise ratio (SNR) without sacrificing the speed and plenty of hardware. The usage of a sub-ranging scheme consists of a coarse SAR ADC followed by an fine ISDM, can not only provide better suppression of the noise added in 2nd stage during conversion but also alleviate the demands of comparator’s resolution in both stages for a given power budget, compared with a conventional Pipelined-SAR ADC. At 1.2 V/1.8 V supply, 33.3 MS/s and 16 MHz input sinusoidal signal in the 40 nm complementary metal oxide semiconductor (CMOS) process, the post-layout simulation results show that the proposed hybrid ADC achieves a signal-to-noise distortion ratio (SNDR) and a spurious free dynamic range (SFDR) of 86.3 dB and 102.5 dBc respectively with a total power consumption of 19.2 mW.

scholarly journals Influence of Analog-To-Digital Conversion and Decimation Parameters on the Signal-To-Noise Ratio in the Radar Path

2021 ◽  
Vol 24 (6) ◽  
pp. 38-50
Author(s):  
S. R. Heister ◽  
V. V. Kirichenko
Keyword(s):  
Signal To Noise Ratio ◽  
Sampling Rate ◽  
Quantization Noise ◽  
Least Significant Bit ◽  
Signal To Noise ◽  
Analog To Digital ◽  
Noise Interference ◽  
Analog To Digital Conversion ◽  
Wide Range ◽  
Noise Ratio

Introduction. The digital representation of received radar signals has provided a wide range of opportunities for their processing. However, the used hardware and software impose some limits on the number of bits and sampling rate of the signal at all conversion and processing stages. These limitations lead to a decrease in the signal-to-interference ratio due to quantization noise introduced by powerful components comprising the received signal (interfering reflections; active noise interference), as well as the attenuation of a low-power reflected signal represented by a limited number of bits. In practice, the amplitude of interfering reflections can exceed that of the signal reflected from the target by a factor of thousands.Aim. In this connection, it is essential to take into account the effect of quantization noise on the signal-tointerference ratio.Materials and methods. The article presents expressions for calculating the power and power spectral density (PSD) of quantization noise, which take into account the value of the least significant bit of an analog-to-digital converter (ADC) and the signal sampling rate. These expressions are verified by simulating 4-, 8- and 16-bit ADCs in the Mathcad environment.Results. Expressions are derived for calculating the quantization noise PSD of interfering reflections, which allows the PSD to be taken into account in the signal-to-interference ratio at the output of the processing chain. In addition, a comparison of decimation options (by discarding and averaging samples) is performed drawing on the estimates of the noise PSD and the signal-to-noise ratio.Conclusion. Recommendations regarding the ADC bit depth and sampling rate for the radar receiver are presented.

A LOW POWER 13-BIT 50MS/s RECIRCULATING PIPELINE ANALOG TO DIGITAL CONVERTER

2014 ◽  
Vol 23 (06) ◽  
pp. 1450090 ◽  
Author(s):  
ARASH ESMAILI ◽  
HADISEH BABAZADEH ◽  
KHAYROLLAH HADIDI ◽  
ABDOLLAH KHOEI
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Cmos Technology ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Nyquist Frequency ◽  
Signal To Noise ◽  
Analog To Digital ◽  
Spurious Free Dynamic Range ◽  
Free Dynamic

A 13-bit analog-to-digital converter (ADC) is designed in 0.35 μm CMOS technology that reduces the power consumption through sharing the resources between pipeline stages. Using a dummy sample-and-hold (S/H) and recirculating concept the requirements for the first stage are relaxed and the design restrictions are resolved. This ADC does not use a dedicated S/H and reaches a speed of 50 MS/s. The design is tested with TSMC mixed-signal 0.35 μm technology and post layout simulations shows over 75 dB Signal-to-Noise and Distortion-Ratio (SNDR) and over 85 dB Spurious Free Dynamic Range (SFDR) at the Nyquist frequency. The designed chip occupies an area of 1.3 mm–0.7 mm and consumes 164 mW power at Nyquist from a 3.3 V supply.

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