A LOW POWER 13-BIT 50MS/s RECIRCULATING PIPELINE ANALOG TO DIGITAL CONVERTER

2014 ◽  
Vol 23 (06) ◽  
pp. 1450090 ◽  
Author(s):  
ARASH ESMAILI ◽  
HADISEH BABAZADEH ◽  
KHAYROLLAH HADIDI ◽  
ABDOLLAH KHOEI
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Cmos Technology ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Nyquist Frequency ◽  
Signal To Noise ◽  
Analog To Digital ◽  
Spurious Free Dynamic Range ◽  
Free Dynamic

A 13-bit analog-to-digital converter (ADC) is designed in 0.35 μm CMOS technology that reduces the power consumption through sharing the resources between pipeline stages. Using a dummy sample-and-hold (S/H) and recirculating concept the requirements for the first stage are relaxed and the design restrictions are resolved. This ADC does not use a dedicated S/H and reaches a speed of 50 MS/s. The design is tested with TSMC mixed-signal 0.35 μm technology and post layout simulations shows over 75 dB Signal-to-Noise and Distortion-Ratio (SNDR) and over 85 dB Spurious Free Dynamic Range (SFDR) at the Nyquist frequency. The designed chip occupies an area of 1.3 mm–0.7 mm and consumes 164 mW power at Nyquist from a 3.3 V supply.

scholarly journals Effects of ADC Nonlinearity on the Spurious Dynamic Range Performance of Compressed Sensing

2014 ◽  
Vol 2014 ◽  
pp. 1-6 ◽  
Author(s):  
Rongzong Kang ◽  
Pengwu Tian ◽  
Hongyi Yu
Keyword(s):  
Compressed Sensing ◽  
Dynamic Range ◽  
Dynamic Performance ◽  
Digital Converter ◽  
Analog To Digital ◽  
Sensing System ◽  
Spurious Free Dynamic Range ◽  
Simulation Results ◽  
The Impact ◽  
Free Dynamic

Analog-to-information converter (AIC) plays an important role in the compressed sensing system; it has the potential to significantly extend the capabilities of conventional analog-to-digital converter. This paper evaluates the impact of AIC nonlinearity on the dynamic performance in practical compressed sensing system, which included the nonlinearity introduced by quantization as well as the circuit non-ideality. It presents intuitive yet quantitative insights into the harmonics of quantization output of AIC, and the effect of other AIC nonlinearity on the spurious dynamic range (SFDR) performance is also analyzed. The analysis and simulation results demonstrated that, compared with conventional ADC-based system, the measurement process decorrelates the input signal and the quantization error and alleviate the effect of other decorrelates of AIC, which results in a dramatic increase in spurious free dynamic range (SFDR).

scholarly journals Design & Implementation of Low Power 3-bit Flash ADC in 0.18μm CMOS

2012 ◽  
pp. 89-93
Author(s):  
Pradeep Kumar ◽  
Amit Kolhe
Keyword(s):  
Power Consumption ◽  
Response Time ◽  
Low Power ◽  
Cmos Technology ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Chip Area ◽  
Flash Adc ◽  
Analog To Digital ◽  
Design And Implementation

This paper describes the design and implementation of a Low Power 3-bit flash Analog to Digital converter (ADC). It includes 7 comparators and one thermometer to binary encoder. It is implemented in 0.18um CMOS Technology. The presimulation of ADC is done in T-Spice and post layout simulation is done in Microwind3.1. The response time of the comparator equal to 6.82ns and for Flash ADC as 18.77ns.The Simulated result shoes the power consumption in Flash ADC as is 36.273mw .The chip area is for Flash ADC is 1044um2 .

Design of Low Power and High Precision Successive Approximation Register Analog-to-Digital Converter (SAR-ADC) Based on Piecewise Capacitance and Calibration Technique

2020 ◽  
Vol 15 (4) ◽  
pp. 478-486
Author(s):  
Sheng-Biao An ◽  
Li-Xin Zhao ◽  
Shi-Cong Yang ◽  
Tao An ◽  
Rui-Xia Yang
Keyword(s):  
Power Consumption ◽  
Successive Approximation ◽  
Dynamic Range ◽  
Sar Adc ◽  
Total Power ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Successive Approximation Register ◽  
Total Power Consumption

This paper presents a charge redistributed successive approximation register analog-to-digital converter (SAR ADC). Compared with the traditional Digital-Analog Convertor (DAC), the power consumption of the DAC scheme is reduced by 90%, the area is reduced by 60%. The test chip fabricated in 180 nm Complementary Metal Oxide Semiconductor (CMOS) occupied an active area of 0.12 mm 2 . At 10 MS/s, a signal-to-noise and distortion ratio (SNDR) of 57.70 dB and a spurious-free dynamic range (SFDR) of 55.63 dB are measured with 1.68 Vpp differential-mode input signal. The total power consumption is 690 μW corresponding to 67 fJ/conversion step figure of merit.

Design of Low Voltage Low Power ADC for WSN Node

2013 ◽  
Vol 760-762 ◽  
pp. 561-566
Author(s):  
Si Kui Ren ◽  
Zhi Qun Li
Keyword(s):  
Low Power ◽  
Figure Of Merit ◽  
Dynamic Range ◽  
Low Voltage ◽  
Cmos Technology ◽  
Total Power ◽  
Chip Area ◽  
Analog To Digital ◽  
Spurious Free Dynamic Range ◽  
Free Dynamic

This paper presents a low power low voltage 7bit 16MS/s SAR ADC (successive approximation register analog-to-digital converter) for the application of ZigBee receiver. The proposed 7-bit ADC is designed and simulated in 180nm RF CMOS technology. Post simulation results show that at 1.0-V supply and 16 MS/s, the ADC achieves a SNDR (signal-to-noise-and-distortion ratio) and SFDR (Spurious Free Dynamic Range) are 43.6dB, 57.4dB respectively. The total power dissipation is 228μW, and it occupies a chip area of 0.525 mm2. It results in a figure-of-merit (FOM) of 0.11pJ/step.

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