Dual Port RAM MBIST Failure Analysis Using Time Resolved Dynamic Laser Stimulation

Author(s):  
Jonathan Shaw ◽  
Christopher McMahon ◽  
Yin Shyang Ng ◽  
Félix Beaudoi

Abstract This paper presents the use of Dynamic Laser Stimulation (DLS) and Time-Resolved DLS (TR-DLS) to provide fail site localization and complementary information on a failed embedded memory IC. In this study, an embedded dual port RAM within a 90nm IC that failed one of the Memory Built-In Self Tests (MBISTs) was investigated. This technique rapidly localized the failing area within the memory read/write circuitry. The TR-DLS provided maps for each operation of the MBIST pattern. With this information, the failure was clearly identified as a read operation failure. The TR-DLS technique also provided much refined site signature (down to just one net) within the sense amp of the Port B of the dual port RAM. This information provided very specific indication on how to improve the operation of that particular sense amp circuitry within the dual port RAM Memory.

Author(s):  
Thomas Ziemann ◽  
Alexander Tsibizov ◽  
Bhagyalakshmi Kakarla ◽  
Lorenz Bort ◽  
Ulrike Grossner

2011 ◽  
Vol 51 (9-11) ◽  
pp. 1658-1661 ◽  
Author(s):  
R. Llido ◽  
J. Gomez ◽  
V. Goubier ◽  
N. Froidevaux ◽  
L. Dufayard ◽  
...  

Author(s):  
Felix Beaudoin ◽  
Satish Kodali ◽  
Rohan Deshpande ◽  
Wayne Zhao ◽  
Edmund Banghart ◽  
...  

Abstract Fault localization using both dynamic laser stimulation and emission microscopy was used to localize the failing transistors within the failing scan chain latch on multiple samples. Nanoprobing was then performed and the source to drain leakage in N-type FinFETs was identified. After extensive detailed characterization, it was concluded that the N-type dopant signal was likely due to projections from the source/drain regions included in the TEM lamella. Datamining identified the scan chain fail to be occurring uniquely for a specific family of tools used during source/drain implant diffusion activation. This paper discusses the processes involved in yield delta datamining of FinFET and its advantages over failure characterization, fault localization, nanoprobing, and physical failure analysis.


2008 ◽  
Vol 48 (8-9) ◽  
pp. 1529-1532 ◽  
Author(s):  
M. Sienkiewicz ◽  
P. Perdu ◽  
A. Firiti ◽  
K. Sanchez ◽  
O. Crepel ◽  
...  

Author(s):  
A. Firiti ◽  
D. Lewis ◽  
F. Beaudoin ◽  
P. Perdu ◽  
G. Haller ◽  
...  

Author(s):  
J.G. van Hassel ◽  
F. Zachariasse

Abstract In new product designs increasing effort is needed to observe and prove failure mechanisms or process marginalities. For advanced failure analysis Soft Defect Localization (SDL) [1] and Time Resolved Emission (TRE) [2,3] have now become a standard analysis method. Both techniques require a close co-operation between designers and analysts. In this paper we will discuss a comprehensive study to find the mechanism behind a speed problem in the digital part of an audio signal processor. The additional delay was related to unwanted routing through poly-silicide in timing critical circuitry.


2006 ◽  
Vol 46 (9-11) ◽  
pp. 1514-1519 ◽  
Author(s):  
A. Douin ◽  
V. Pouget ◽  
M. De Matos ◽  
D. Lewis ◽  
P. Perdu ◽  
...  

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