A New Failure Analysis Roadmap for Power Semiconductor Modules and Devices

2011 ◽  
Author(s):  
Peter Jacob ◽  
Albert Kunz ◽  
Giovanni Nicoletti
Keyword(s):  
Failure Analysis ◽  
High Dose ◽  
Power Semiconductors ◽  
Power Semiconductor ◽  
Metal Layers ◽  
Failure Localization

Abstract In case of power semiconductor analysis, classical failure localization methods are restricted in application due to thick, closed metal layers and high-dose bulk-Si implants, making backside access difficult. Furthermore, defect traces in power semiconductors are often such severe that no conclusive FA is possible anymore. The new roadmap considers these specialties and shows ways how to deal with them, showing ways to conclusive results.

SRAM Failure Analysis Strategy

2003 ◽  
Author(s):  
P. Egger ◽  
C. Burmer
Keyword(s):  
Liquid Crystal ◽  
Failure Analysis ◽  
The Other ◽  
Other Hand ◽  
Analysis Strategy ◽  
Emission Microscopy ◽  
Metal Layers ◽  
Failure Localization

Abstract The area of embedded SRAMs in advanced logic ICs is increasing more and more. On the other hand smaller structure sizes and an increasing number of metal layers make conventional failure localization by using emission microscopy or liquid crystal inefficient. In this paper a SRAM failure analysis strategy will be presented independent on layout and technology.

Analysis of Delta Iddq Soft Fails on Pass Chips

2006 ◽  
Author(s):  
I. Österreicher ◽  
S. Eckl ◽  
B. Tippelt ◽  
S. Döring ◽  
R. Prang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Mode ◽  
Photon Emission ◽  
Complete Analysis ◽  
Functional Tests ◽  
Analysis Techniques ◽  
Atomic Force ◽  
Current Consumption ◽  
Emission Microscopy ◽  
Failure Localization

Abstract Depending on the field of application the ICs have to meet requirements that differ strongly from product to product, although they may be manufactured with similar technologies. In this paper a study of a failure mode is presented that occurs on chips which have passed all functional tests. Small differences in current consumption depending on the state of an applied pattern (delta Iddq measurement) are analyzed, although these differences are clearly within the usual specs. The challenge to apply the existing failure analysis techniques to these new fail modes is explained. The complete analysis flow from electrical test and Global Failure Localization to visualization is shown. The failure is localized by means of photon emission microscopy, further analyzed by Atomic Force Probing, and then visualized by SEM and TEM imaging.

Application of Fast Laser Deprocessing Techniques in Physical Failure Analysis on SRAM Memory of Advance Technology

2014 ◽  
Author(s):  
H.H. Yap ◽  
P.K. Tan ◽  
G.R. Low ◽  
M.K. Dawood ◽  
H. Feng ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Cost Effective ◽  
Tetraethyl Orthosilicate ◽  
Ic Design ◽  
Advance Technology ◽  
Defect Identification ◽  
Technology Scaling ◽  
And Function ◽  
Metal Layers

Abstract With technology scaling of semiconductor devices and further growth of the integrated circuit (IC) design and function complexity, it is necessary to increase the number of transistors in IC’s chip, layer stacks, and process steps. The last few metal layers of Back End Of Line (BEOL) are usually very thick metal lines (>4μm thickness) and protected with hard Silicon Dioxide (SiO2) material that is formed from (TetraEthyl OrthoSilicate) TEOS as Inter-Metal Dielectric (IMD). In order to perform physical failure analysis (PFA) on the logic or memory, the top thick metal layers must be removed. It is time-consuming to deprocess those thick metal and IMD layers using conventional PFA workflows. In this paper, the Fast Laser Deprocessing Technique (FLDT) is proposed to remove the BEOL thick and stubborn metal layers for memory PFA. The proposed FLDT is a cost-effective and quick way to deprocess a sample for defect identification in PFA.

scholarly journals Infrared Thermography applied to power electron devices investigation

2015 ◽  
Vol 28 (2) ◽  
pp. 205-212 ◽  
Author(s):  
Giovanni Breglio ◽  
Andrea Irace ◽  
Luca Maresca ◽  
Michele Riccio ◽  
Gianpaolo Romano ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Infrared Thermography ◽  
Semiconductor Devices ◽  
Electronic Devices ◽  
Experimental Characterization ◽  
Ir Thermography ◽  
Power Semiconductor ◽  
Power Semiconductor Devices ◽  
Electron Devices ◽  
Lock In

The aim of this paper is to give a presentation of the principal applications of Infrared Thermography for analysis and testing of electrondevices. Even though experimental characterization could be carried out on almost any electronic devices and circuits, here IR Thermography for investigation of power semiconductor devices is presented. Different examples of functional and failure analysis in both transient and lock-in modes will be reported.

scholarly journals The current status of power semiconductors

2015 ◽  
Vol 28 (2) ◽  
pp. 193-203 ◽  
Author(s):  
Jan Vobecký
Keyword(s):  
Functional Performance ◽  
Wide Bandgap ◽  
Current Status ◽  
Design And Technology ◽  
Power Sector ◽  
Power Semiconductors ◽  
Power Semiconductor ◽  
Power Semiconductor Devices ◽  
Silicon Devices

Trends in the design and technology of power semiconductor devices are discussed on the threshold of the year 2015. Well established silicon technologies continue to occupy most of applications thanks to the maturity of switches like MOSFET, IGBT, IGCT and PCT. Silicon carbide (SiC) and gallium nitride (GaN) are striving to take over that of the silicon. The most relevant SiC device is the MPS (JBS) diode, followed by MOSFET and JFET. GaN devices are represented by lateral HEMT. While the long term reliability of silicon devices is well trusted, the SiC MOSFETs and GaN HEMTs are struggling to achieve a similar confidence. Two order higher cost of SiC equivalent functional performance at device level limits their application to specific cases, but their number is growing. Next five years will therefore see the co-existence of these technologies. Silicon will continue to occupy most of applications and dominate the high-power sector. The wide bandgap devices will expand mainly in the 600 - 1200 V range and dominate the research regardless of the voltage class.

Manual Assembly of 400um Bumped-Die GaN Power Semiconductor Devices

2012 ◽  
Vol 2012 (1) ◽  
pp. 000514-000523
Author(s):  
Stephan W. Henning ◽  
Luke Jenkins ◽  
Sidni Hale ◽  
Christopher G. Wilson ◽  
John Tennant ◽  
...  
Keyword(s):  
Semiconductor Devices ◽  
Thermal Dissipation ◽  
Single Digit ◽  
Manual Assembly ◽  
Power Semiconductors ◽  
Power Semiconductor ◽  
Residue Removal ◽  
Power Semiconductor Devices ◽  
Package Size ◽  
The Cost

Until recently, power semiconductors were usually produced as TO, power-PAK, and D-PAK style packaging, due to die size, thermal dissipation requirements, and the vertical flow of current through the devices. The introduction of GaN to power semiconductors has allowed manufactures to produce devices with approximately 9% the footprint of similar rated D-PAK Si MOSFETs. In addition, GaN semiconductors have much better theoretical limits of specific on-resistance to breakdown voltage, when compared to Si and SiC. As of now, GaN devices offer very good performance at much less the cost of SiC, very small footprints, no reverse recovery losses of a body diode, very low RDS(ON), and very fast turn-on and turn-off times due to QGS in single-digit nC range. GaN semiconductors are expected to make vast improvements over the next decade. Unfortunately, this decrease in package size has made design prototyping significantly more challenging. Traditional manual solder iron assembly is not sufficient for these devices. Difficulties include board design, device handling, alignment, solder reflow, flux residue removal, and post-assembly inspection. The EPC 2014 and 2015 devices both have a 4mm pitch and are 1.85mm2 and 6.70mm2, respectively. In many situations, the decreased pitch and small overall size of these devices mandate the use of automated assembly equipment, such as a pick & place, to ensure quality and repeatability of assembly. However, this may not be feasible for initial prototyping, due to cost and time constraints. Here we will present a technique for manual assembly of these chip scale devices, applied specifically to the EPC 2014 and 2015. This should decrease the cost and turn time for prototype assembly when utilizing these types of chip scale packaged power semiconductor devices.

Non-linear failure analysis of HCPB blanket for DEMO taking into account high dose irradiation

2014 ◽  
Vol 89 (7-8) ◽  
pp. 1664-1668 ◽  
Author(s):  
J. Aktaa ◽  
S. Kecskés ◽  
P. Pereslavtsev ◽  
U. Fischer ◽  
L.V. Boccaccini
Keyword(s):  
Failure Analysis ◽  
High Dose ◽  
Dose Irradiation ◽  
Non Linear

scholarly journals Wafer Container Monitoring Concerning Airborne Molecular Contaminations along a 300 mm Power Semiconductor Production Flow

2021 ◽  
Vol 314 ◽  
pp. 41-46
Author(s):  
Peter Franze ◽  
Germar Schneider ◽  
Stefan Kaskel
Keyword(s):  
High Volume ◽  
Yield Losses ◽  
Production Flow ◽  
Power Semiconductors ◽  
Power Semiconductor ◽  
New Concepts ◽  
Semiconductor Production

The focus of the study was to understand the behavior of airborne molecular contaminations (AMC) within the 300 mm wafer containers called front-opening unified pods (FOUPs) in a high-volume fabrication facility for power semiconductors of Infineon Technologies Dresden. A main goal was to implement new concepts and strategies to prevent the different power semiconductors from any yield losses driven by AMC. It could be shown, that there is a strong dependency of the concentration and the type of the determined contaminations on the investigated process steps.

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