Failure Analysis of CDM-ESD Damage in a GaAs RFIC

2000 ◽  
Author(s):  
Amy Poe ◽  
Steve Brockett ◽  
Tony Rubalcava
Keyword(s):  
Radio Frequency ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Production Test ◽  
Analysis Techniques ◽  
Device Model ◽  
Charged Device ◽  
Subsequent Failure

Abstract The intent of this work is to demonstrate the importance of charged device model (CDM) ESD testing and characterization by presenting a case study of a situation in which CDM testing proved invaluable in establishing the reliability of a GaAs radio frequency integrated circuit (RFIC). The problem originated when a sample of passing devices was retested to the final production test. Nine of the 200 sampled devices failed the retest, thus placing the reliability of all of the devices in question. The subsequent failure analysis indicated that the devices failed due to a short on one of two capacitors, bringing into question the reliability of the dielectric. Previous ESD characterization of the part had shown that a certain resistor was likely to fail at thresholds well below the level at which any capacitors were damaged. This paper will discuss the failure analysis techniques which were used and the testing performed to verify the failures were actually due to ESD, and not caused by weak capacitors.

Advanced IR-OBIRCH Analysis Technique for High Isb Failure Analysis

2010 ◽  
Author(s):  
Kuo Hsiung Chen ◽  
Wen Sheng Wu ◽  
Yu Hsiang Shu ◽  
Jian Chan Lin
Keyword(s):  
Failure Analysis ◽  
Failure Mechanisms ◽  
Fault Localization ◽  
Resistance Change ◽  
The Real ◽  
Analysis Techniques ◽  
Analysis Technique ◽  
Leakage Failure ◽  
Failure Site

Abstract IR-OBIRCH (Infrared Ray – Optical Beam Induced Resistance Change) is one of the main failure analysis techniques [1] [2] [3] [4]. It is a useful tool to do fault localization on leakage failure cases such as poor Via or contact connection, FEoL or BEoL pattern bridge, and etc. But the real failure sites associated with the above failure mechanisms are not always found at the OBIRCH spot locations. Sometimes the real failure site is far away from the OBIRCH spot and it will result in inconclusive PFA Analysis. Finding the real failure site is what matters the most for fault localization detection. In this paper, we will introduce one case using deep sub-micron process generation which suffers serious high Isb current at wafer donut region. In this case study a BEoL Via poor connection is found far away from the OBIRCH spots. This implies that layout tracing skill and relation investigation among OBIRCH spots are needed for successful failure analysis.

Failure Analysis of Advanced Microprocessors through Backside Approaches

1998 ◽  
Author(s):  
D. Davis ◽  
O. Diaz de Leon ◽  
L. Hughes ◽  
S. V. Pabbisetty ◽  
R. Parker ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Preparation Methods ◽  
Analysis Techniques ◽  
Analytical Approaches ◽  
Sample Preparation Methods ◽  
New Devices

Abstract The advent of Flip Chip and other complex package configurations and process technologies have made conventional failure analysis techniques inapplicable. This paper covers the ways in which conventional techniques have been modified to meet the FA challenges presented by these new devices – specifically, by forcing analysis to be done from the backside of the device. Modifications to the traditional FA process steps, including new sample preparation methods, changes in hardware, and alterations to physical failure analysis processes are described. To demonstrate the use of backside analytical approaches, some examples of applications and a case study are also included.

Complementary Optical Techniques for Advanced IC Failure Analysis – Case Study

2005 ◽  
Author(s):  
Joy Y. Liao ◽  
Howard Lee Marks ◽  
Herve Deslandes
Keyword(s):  
Failure Analysis ◽  
Optical Techniques ◽  
Analysis Techniques ◽  
Diagnostic Time

Abstract We investigated and demonstrated the advantages and limitations of several optical methodologies as valuable silicon failure analysis techniques, and how they could be used in a complementary manner to assist in shortening the diagnostic time.

Extended Circuit Edit, Analysis and Trimming Capabilities Based on the Backside Focused Ion Beam Created Ultra Thin Silicon Platform

2009 ◽  
Author(s):  
Rudolf Schlangen ◽  
Rainer Leihkauf ◽  
Uwe Kerst ◽  
Christian Boit ◽  
Peter Egger ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Device Performance ◽  
Integrated Circuit Design ◽  
Analysis Techniques ◽  
Design Changes ◽  
Almost All ◽  
Critical Regions

Abstract Highly integrated microelectronic devices drive an ever increasing effort in engineering, manufacturing and failure analysis. Almost all established failure analysis techniques and conventional circuit edit procedures are facing the severe challenges and limits of aggressive downscaling. While device design and manufacturing cooperate closely, failure analysis often is considered as an add-on service upon request. If physical limitations are hard to overcome, extending the application of an established method to promote synergy with other aspects of IC making is one option for future progress. Traditionally circuit edit FIB is a post-fix procedure to allow for fast design changes in the wiring of a chip. Device performance remains unchanged. A different aspect is the deposition of FIB probe pads which permits electrical probing in locations difficult to reach. Probing results in critical regions of a circuit provide tremendous value for general debug or first silicon analysis. Device performance can be monitored. This paper adds a another dimension with new CE and functional chip analysis techniques where device performance can be directly monitored and altered; therefore connecting integrated circuit design, device development and failure analysis for shorter development cycles.

UTC Clinic Hospital Network: Description of International Network of Failure Analysis Labs and Case Studies

2000 ◽  
Author(s):  
Timothy C. Wilkins
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Lessons Learned ◽  
Mechanical Failure ◽  
International Network ◽  
Analysis Techniques ◽  
Organization Process ◽  
Common Problems ◽  
Clinic Hospital

Abstract This paper describes the organization, process, and challenges of an international network of electrical and mechanical failure analysis labs that leverage lessons learned, resources, failure analysis techniques, and benchmarking of current common problems. Formed 11 years ago as just an electrical/electronic part failure analysis council within Otis Elevator and Carrier, this group has grown to be a network of 16 electrical and 22 mechanical labs. This council is a one of a kind network that also includes suppliers of parts to UTC. This paper will also illustrate the advantages of cross-functional and divisional leveraging with case study examples.

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