scholarly journals Design of a time-mode analog-to-digital converter utilizing a time-to-digital converter that is scalable with CMOS technology

2019 ◽  
Author(s):  
◽  
Jian Sen Teh
Keyword(s):  
Cmos Technology ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Time To Digital Converter

An 8-Bit Flash Analog-to-Digital Converter in Standard CMOS Technology Functional From 4.2 K to 300 K

2009 ◽  
Vol 44 (7) ◽  
pp. 2019-2025 ◽  
Author(s):  
Ybe Creten ◽  
Patrick Merken ◽  
Willy Sansen ◽  
Robert P. Mertens ◽  
Chris Van Hoof
Keyword(s):  
Cmos Technology ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital

scholarly journals A 1.2 V, 8-bit, 100 MHz pipelined analog-to-digital converter

2021 ◽  
Author(s):  
Shahab Ardalan
Keyword(s):  
Power Dissipation ◽  
Low Voltage ◽  
Low Power Design ◽  
Cmos Technology ◽  
Total Power ◽  
Cable Modem ◽  
Analog To Digital Converter ◽  
Flat Panel Display ◽  
Digital Converter ◽  
Analog To Digital

A 1.2 V, 8 bit, 100 MSample/Sec Pipeline Analog-to-Digital Converter is designed in 0.18-μm standard CMOS technology. An emphasis was placed on observing the low voltage and low power design. The architecture of this ADC is 1 bit/stage pipelined configuration. With above specifications the designed ADC can be applicable for DVI flat-panel display; Giga bit Ethernet on copper, RGB to LCD converter and cable modem. This designed ADC can achieve SNDR 56dB in 100 MHz sampling frequency with 8 bit resolution. Total power dissipation is 40.6mW and INL is around 1 LSB and the maximum swing of the input is 1 Volt peak to peak which is almost rail-to-rail situation. The core area of the ADC excluding pads is around 0.25mm 2 .

scholarly journals Design & Implementation of Low Power 3-bit Flash ADC in 0.18μm CMOS

2012 ◽  
pp. 89-93
Author(s):  
Pradeep Kumar ◽  
Amit Kolhe
Keyword(s):  
Power Consumption ◽  
Response Time ◽  
Low Power ◽  
Cmos Technology ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Chip Area ◽  
Flash Adc ◽  
Analog To Digital ◽  
Design And Implementation

This paper describes the design and implementation of a Low Power 3-bit flash Analog to Digital converter (ADC). It includes 7 comparators and one thermometer to binary encoder. It is implemented in 0.18um CMOS Technology. The presimulation of ADC is done in T-Spice and post layout simulation is done in Microwind3.1. The response time of the comparator equal to 6.82ns and for Flash ADC as 18.77ns.The Simulated result shoes the power consumption in Flash ADC as is 36.273mw .The chip area is for Flash ADC is 1044um2 .

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