scholarly journals Execution Model to Reduce the Interference of Shared Memory in ARINC 653 Compliant Multicore RTOS

2020 ◽  
Vol 10 (7) ◽  
pp. 2464
Author(s):  
Sihyeong Park ◽  
Mi-Young Kwon ◽  
Hoon-Kyu Kim ◽  
Hyungshin Kim
Keyword(s):  
Execution Time ◽  
Software Verification ◽  
Main Memory ◽  
Critical Systems ◽  
Multicore Architectures ◽  
L2 Cache ◽  
Execution Model ◽  
Time Division ◽  
L1 And L2 ◽  
Execution Models

Multicore architecture is applied to contemporary avionics systems to deal with complex tasks. However, multicore architectures can cause interference by contention because the cores share hardware resources. This interference reduces the predictable execution time of safety-critical systems, such as avionics systems. To reduce this interference, methods of separating hardware resources or limiting capacity by core have been proposed. Existing studies have modified kernels to control hardware resources. Additionally, an execution model has been proposed that can reduce interference by adjusting the execution order of tasks without software modification. Avionics systems require several rigorous software verification procedures. Therefore, modifying existing software can be costly and time-consuming. In this work, we propose a method to apply execution models proposed in existing studies without modifying commercial real-time operating systems. We implemented the time-division multiple access (TDMA) and acquisition execution restitution (AER) execution models with pseudo-partition and message queuing on VxWorks 653. Moreover, we propose a multi-TDMA model considering the characteristics of the target hardware. For the interference analysis, we measured the L1 and L2 cache misses and the number of main memory requests. We demonstrated that the interference caused by memory sharing was reduced by at least 60% in the execution model. In particular, multi-TDMA doubled utilization compared to TDMA and also reduced the execution time by 20% compared to the AER model.

Fuzzy Logic-Based DSE Engine: Reconfiguration for Optimization of Multicore Architectures

2016 ◽  
Vol 25 (12) ◽  
pp. 1650160
Author(s):  
Iqra Farhat ◽  
Muhammad Yasir Qadri ◽  
Nadia N. Qadri ◽  
Jameel Ahmed
Keyword(s):  
Fuzzy Logic ◽  
Energy Consumption ◽  
Design Space Exploration ◽  
Design Space ◽  
Multicore Architectures ◽  
L2 Cache ◽  
On Chip ◽  
L1 And L2 ◽  
The Impact ◽  
Target Design

Moore’s law has been one of the reason behind the evolution of multicore architectures. Modern multicore architectures offer great amount of parallelism and on-chip resources that remain underutilized. This is partly due to inefficient resource allocation by operating system or application being executed. Consequently the poor resource utilization results in greater energy consumption and less throughput. This paper presents a fuzzy logic-based design space exploration (DSE) approach to reconfigure a multicore architecture according to workload requirements. The target design space is explored for L1 and L2 cache size and associativity, operating frequency, and number of cores, while the impact of various configurations of these parameters is analyzed on throughput, miss ratios for L1 and L2 cache and energy consumption. MARSSx86, a cycle accurate simulator, running various SPALSH-2 benchmark applications has been used to evaluate the architecture. The proposed fuzzy logic-based DSE approach resulted in reduction in energy consumption along with an overall improved throughput of the system.

Interface Risk Reduction in an Integrated SURF-SPS Scope Execution

2021 ◽  
Author(s):  
Hemant Priyadarshi ◽  
Daniel Nickel ◽  
Seban Jose
Keyword(s):  
Risk Reduction ◽  
Qualitative Comparison ◽  
The Matrix ◽  
Execution Model ◽  
Execution Models

Abstract The paper provides a detailed estimation of the interfaces that exist in a split SURF-SPS execution model and provides a qualitative comparison to an integrated SURF-SPS execution model. A comprehensive matrix of dependencies between SURF and SPS is presented and is categorized into engineering, procurement, construction/fabrication and installation work packages. The matrix is used to illustrate the exact scope dependencies and thus, the sources of interfaces. A hypothetical greenfield development has been assumed to develop the interface matrix and to use it for comparison of the two execution models. The comparison also reveals how interfaces are naturally eliminated in an integrated SURF-SPS execution model. In each of the workstreams (E-P-C-I), top risks have been identified and monetary liability estimates for those risks have been provided. By transfer of these risks from company to contractor, monetary liability gets transferred to the contractor, thus, resulting in significant savings for operating companies. The following tangible results are provided in the paper: a) % of interface(s) reduced in the E-P-C-I areas; b) Risk reduction in monetary terms for operators – estimated values. This paper justifies the fact that there is a significant interface scope and risk reduction for operators, if they adopt an integrated SURF-SPS execution model.

Designing of High Performance Multicore Processor with Improved Cache Configuration and Interconnect

2016 ◽  
pp. 204-219
Author(s):  
Ram Prasad Mohanty ◽  
Ashok Kumar Turuk ◽  
Bibhudatta Sahoo
Keyword(s):  
High Performance ◽  
Multicore Processors ◽  
Multicore Processor ◽  
Cache Size ◽  
L2 Cache ◽  
Internal Network ◽  
On Chip ◽  
L1 And L2 ◽  
The Impact ◽  
Cache Configuration

The growing number of cores increases the demand for a powerful memory subsystem which leads to enhancement in the size of caches in multicore processors. Caches are responsible for giving processing elements a faster, higher bandwidth local memory to work with. In this chapter, an attempt has been made to analyze the impact of cache size on performance of Multi-core processors by varying L1 and L2 cache size on the multicore processor with internal network (MPIN) referenced from NIAGRA architecture. As the number of core's increases, traditional on-chip interconnects like bus and crossbar proves to be low in efficiency as well as suffer from poor scalability. In order to overcome the scalability and efficiency issues in these conventional interconnect, ring based design has been proposed. The effect of interconnect on the performance of multicore processors has been analyzed and a novel scalable on-chip interconnection mechanism (INOC) for multicore processors has been proposed. The benchmark results are presented by using a full system simulator. Results show that, using the proposed INoC, compared with the MPIN; the execution time are significantly reduced.

Online monitoring for safety-critical multicore systems

2017 ◽  
Vol 59 (5) ◽  
Author(s):  
Sebastian Tobuschat ◽  
Adam Kostrzewa ◽  
Falco K. Bapp ◽  
Christoph Dropmann
Keyword(s):  
Multicore Processors ◽  
Normal System ◽  
Critical Systems ◽  
Multicore Architectures ◽  
System Behavior ◽  
Multicore Systems ◽  
Safety Critical ◽  
System A ◽  
Software Execution ◽  
System Configurations

AbstractUsing multicore processors in safety-critical systems is a challenge as well as an opportunity. The real parallelism, which may affect synchronization and determinism, leads to a safety-challenge, because new possible interferences might arise. Additionally, redundant software execution is possible within multicore systems. In complex multicore architectures one of the most important challenges is to know the system behavior and the recognition of any variations from the normal system behavior has to be guaranteed. For those cases it is necessary to monitor several states of the system, configurations, timing, etc. To monitor such a complex system a lot of information from the inside of the system needs to be evaluated without affecting the rest of the MPSoC.

A HYBRID SHARED MEMORY EXECUTION MODEL FOR A DATA PARALLEL LANGUAGE WITH I/O

2008 ◽  
Vol 18 (01) ◽  
pp. 23-37 ◽  
Author(s):  
CLEMENS GRELCK ◽  
STEFFEN KUTHE ◽  
SVEN-BODO SCHOLZ
Keyword(s):  
Program Analysis ◽  
Flow Characteristics ◽  
Parallel Execution ◽  
Parallel Language ◽  
Data Parallel ◽  
Execution Model ◽  
Execution Mode ◽  
Parallel Code ◽  
Execution Models ◽  
Compilation Techniques

We propose a novel execution model for the implicitly parallel execution of data parallel programs in the presence of general I/O operations. This model is called hybrid because it combines the advantages of the standard execution models fork/join and SPMD. Based on program analysis the hybrid model adapts itself to one or the other on the granularity of individual instructions. We outline compilation techniques that systematically derive the organization of parallel code from data flow characteristics aiming at the reduction of execution mode switches in general and synchronization/communication requirements in particular. Experiments based on a prototype implementation show the effectiveness of the hybrid execution model for reducing parallel overhead.

A SPLIT L2 DATA CACHE FOR SCALABLE CC-NUMA MULTIPROCESSORS

2005 ◽  
Vol 14 (03) ◽  
pp. 605-617 ◽  
Author(s):  
SUNG WOO CHUNG ◽  
HYONG-SHIK KIM ◽  
CHU SHIK JHON
Keyword(s):  
Execution Time ◽  
Memory Access ◽  
Remote Memory ◽  
Access Time ◽  
Data Cache ◽  
Total Execution Time ◽  
Memory Address ◽  
L2 Cache ◽  
Cache Miss

In scalable CC-NUMA multiprocessors, it is crucial to reduce the average memory access time. For applications where the second-level (L2) cache is large enough, we propose a split L2 cache to utilize the surplus space. The split L2 cache is composed of a traditional LRU cache and an RVC (Remote Victim Cache) which only stores the data of remote memory address range. Thus, it reduces the average L2 cache miss time by keeping remote blocks that would be discarded otherwise. Though the split cache does not reduce the miss rates, it is observed to reduce the total execution time effectively by up to 27%.It even outperform an LRU cache of double size.

scholarly journals ARMv8-A System Semantics: Instruction Fetch in Relaxed Architectures

2020 ◽  
pp. 626-655
Author(s):  
Ben Simner ◽  
Shaked Flur ◽  
Christopher Pulte ◽  
Alasdair Armstrong ◽  
Jean Pichon-Pharabod ◽  
...  
Keyword(s):  
Software Verification ◽  
Critical Systems ◽  
Instruction Sets ◽  
Instruction Fetch ◽  
Robust Model ◽  
Address Translation ◽  
Systems Software ◽  
Hardware Implementations ◽  
Observable Behaviour ◽  
Instruction Caches

AbstractComputing relies on architecture specifications to decouple hardware and software development. Historically these have been prose documents, with all the problems that entails, but research over the last ten years has developed rigorous and executable-as-test-oracle specifications of mainstream architecture instruction sets and “user-mode” concurrency, clarifying architectures and bringing them into the scope of programming-language semantics and verification. However, the system semantics, of instruction-fetch and cache maintenance, exceptions and interrupts, and address translation, remains obscure, leaving us without a solid foundation for verification of security-critical systems software.In this paper we establish a robust model for one aspect of system semantics: instruction fetch and cache maintenance for ARMv8-A. Systems code relies on executing instructions that were written by data writes, e.g. in program loading, dynamic linking, JIT compilation, debugging, and OS configuration, but hardware implementations are often highly optimised, e.g. with instruction caches, linefill buffers, out-of-order fetching, branch prediction, and instruction prefetching, which can affect programmer-observable behaviour. It is essential, both for programming and verification, to abstract from such microarchitectural details as much as possible, but no more. We explore the key architecture design questions with a series of examples, discussed in detail with senior Arm staff; capture the architectural intent in operational and axiomatic semantic models, extending previous work on “user-mode” concurrency; make these models executable as test oracles for small examples; and experimentally validate them against hardware behaviour (finding a bug in one hardware device). We thereby bring these subtle issues into the mathematical domain, clarifying the architecture and enabling future work on system software verification.

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