scholarly journals A Cost-Effective Solution to Improving the Electrical Performance of Metal Contacting Interfaces in IC System under Temperature-Humidity Environment

2019 ◽  
Vol 9 (19) ◽  
pp. 3950
Author(s):  
Li ◽  
Meng ◽  
Shi ◽  
Gao ◽  
Zhang ◽  
...  
Keyword(s):  
Contact Resistance ◽  
Integrated Circuit ◽  
System Reliability ◽  
Cost Effective ◽  
Electrical Performance ◽  
Processing Unit ◽  
Test Results ◽  
Effective Solution ◽  
Central Processing ◽  
Humidity Environment

Temperature-humidity (TH) induced failure mechanism (FM) of metal contacting interfaces in integrated circuit (IC) systems has played a significant role in system reliability issues. This paper focuses on central processing unit (CPU)/motherboard interfaces and studies several factors that are believed to have a great impact on TH performance. They include: Enabling load, surface finish quality, and contacting area. Test vehicles (TVs) of Clarkdale package and of Ibex peak motherboard were designed to measure low level contact resistance (LLCR) for catching any failure. Several sets of design of experiments (DOE) were conducted on 85°C/85% relative humidity and test results were analyzed. A proposal that correlates asperity spots and contact tip design with contact resistance was proposed and thus a cost-effective solution for improving electrical performance under TH was deduced. The proposal has proven to be reasonably effective in practice.

A Practical Method for the Rational Design of Ship Structures

1980 ◽  
Vol 24 (02) ◽  
pp. 101-113 ◽  
Author(s):  
Owen F. Hughes ◽  
Farrokh Mistree ◽  
Vedran Žanic
Keyword(s):  
Optimum Design ◽  
Rational Design ◽  
Cost Effective ◽  
Practical Method ◽  
General Purpose ◽  
Processing Unit ◽  
Ship Structures ◽  
Finite Element Program ◽  
Central Processing ◽  
Element Program

A practical, rationally based method is presented for the automated optimum design of ship structures. The method required the development of (a) a rapid, design-oriented finite-element program for the analysis of ship structures; (b) a comprehensive mathematical model for the evaluation of the capability of the structure; and (c) a cost-effective optimization algorithm for the solution of a large, highly constrained, nonlinear redesign problem. These developments have been incorporated into a program called SHIPOPT. The efficiency and robustness of the method is illustrated by using it to determine the optimum design of a complete cargo hold of a general-purpose cargo ship. The overall dimensions and the design loads are the same as those used in the design of the very successful SD14 series of ships. The redesign problem contains 94 variables, a nonlinear objective function, and over 500 constraints of which approximately half are non-linear. Program SHIPOPT required approximately eight minutes of central processing unit time on a CDC CYBER 171 to determine the optimum design.

scholarly journals Method for improving ripple reduction during phase shedding in multiphase buck converters for SCADA systems

2021 ◽  
Vol 24 (1) ◽  
pp. 29
Author(s):  
Mini P. Varghese ◽  
A. Manjunatha ◽  
T. V. Snehaprabha
Keyword(s):  
Power Supply ◽  
Integrated Circuit ◽  
Buck Converter ◽  
Multiphase System ◽  
Processing Unit ◽  
Central Processing ◽  
Light Load ◽  
Field Programmable ◽  
Ripple Reduction ◽  
Application Specific Integrated Circuit

In the current digital environment, central processing unit (CPUs), field programmable gate array (FPGAs), application-specific integrated circuit (ASICs), as well as peripherals, are growing progressively complex. On motherboards in many areas of computing, from laptops and tablets to servers and Ethernet switches, multiphase phase buck regulators are seen to be more common nowadays, because of the higher power requirements. This study describes a four-stage buck converter with a phase shedding scheme that can be used to power processors in programmable logic controller (PLCs). The proposed power supply is designed to generate a regulated voltage with minimal ripple. Because of the suggested phase shedding method, this power supply also offers better light load efficiency. For this objective, a multiphase system with phase shedding is modeled in MATLAB SIMULINK, and the findings are validated.

A robust system reliability analysis using partitioning and parallel processing of Markov chain

2014 ◽  
Vol 28 (4) ◽  
pp. 311-322 ◽  
Author(s):  
Po Ting Lin ◽  
Yu-Cheng Chou ◽  
Yung Ting ◽  
Shian-Shing Shyu ◽  
Chang-Kuo Chen
Keyword(s):  
Markov Chain ◽  
Parallel Processing ◽  
Reliability Analysis ◽  
System Reliability ◽  
Large Scale ◽  
Transition Probability ◽  
Transition Probability Matrix ◽  
Processing Unit ◽  
Central Processing ◽  
System Reliability Analysis

AbstractThis paper presents a robust reliability analysis method for systems of multimodular redundant (MMR) controllers using the method of partitioning and parallel processing of a Markov chain (PPMC). A Markov chain is formulated to represent the N distinct states of the MMR controllers. Such a Markov chain has N2 directed edges, and each edge corresponds to a transition probability between a pair of start and end states. Because N can be easily increased substantially, the system reliability analysis may require large computational resources, such as the central processing unit usage and memory occupation. By the PPMC, a Markov chain's transition probability matrix can be partitioned and reordered, such that the system reliability can be evaluated through only the diagonal submatrices of the transition probability matrix. In addition, calculations regarding the submatrices are independent of each other and thus can be conducted in parallel to assure the efficiency. The simulation results show that, compared with the sequential method applied to an intact Markov chain, the proposed PPMC can improve the performance and produce allowable accuracy for the reliability analysis on large-scale systems of MMR controllers.

Development of an Automotive Electric Window Control System Based on CAN Bus

2014 ◽  
Vol 602-605 ◽  
pp. 1240-1243 ◽  
Author(s):  
Xu Chen ◽  
Xiao Feng Yin ◽  
Qi Chang Yang ◽  
Han Lu
Keyword(s):  
Control System ◽  
System Reliability ◽  
Can Bus ◽  
Processing Unit ◽  
Application Layer ◽  
Single Chip ◽  
Control Software ◽  
Wiring Harness ◽  
Central Processing ◽  
System A

An electric window control system based on low-speed CAN bus has been developed to reduce the wiring harness of vehicle control system, improve the system reliability and cut overall costs. On the basis of requirement analysis of the control system, a CAN application layer communication protocol has been defined. The electric window control system has been designed using Freescale 16-bit single chip microprocessor MCS12DP256 as central processing unit, and the control software has also been developed, in which an integral algorithm was used to realize the anti-pinch function.

scholarly journals Two-Vehicle Coordination System for Omnidirectional Transportation Based on Image Processing and Deviation Prediction

2021 ◽  
Author(s):  
Huajun Song ◽  
Yanqi Wu ◽  
Yuxing Wu ◽  
Guangbing Zhou ◽  
Chunbo Luo
Keyword(s):  
Image Processing ◽  
Manufacturing Industry ◽  
Cost Effective ◽  
Image Sensor ◽  
Mobile Platform ◽  
Normal Operation ◽  
Processing Unit ◽  
Mobile Platforms ◽  
Central Processing ◽  
Omnidirectional Mobile Platform

AbstractOmnidirectional mobile platform is essential due to its excellent mobility and versatility. With the development of the manufacturing industry, how to transport oversized or overweight goods has become a new problem. Compared with manufacturing omnidirectional mobile platforms with different specifications, it is more cost-effective and flexible to coordinate two non-physically connected omnidirectional platforms to transport overweight and oversized cargo. The roughness of the actual deployment environment and the mechanical deflection between the two vehicles have a significant impact on the normal operation of the system. This paper combines mechanical wheels, image processing algorithms and collaboration algorithms to create a novel and practical split-type omnidirectional mobile platform based on image deviation prediction for transporting oversized or overweighted goods. The proposed system collects raw measurements from a distance sensor and an image sensor, transmits them to a central processing unit through a wireless communication module and calculates and predicts the relative deflection between the two vehicles based on our derived mathematical model. This information is then fed to a Kalman filter and PID control algorithm to coordinate the two vehicles. The effectiveness and performance of our system have been thoroughly tested, which has already been applied in a bullet train production line.

scholarly journals A TensorFlow Extension Framework for Optimized Generation of Hardware CNN Inference Engines

Technologies ◽  
2020 ◽  
Vol 8 (1) ◽  
pp. 6 ◽  
Author(s):  
Vasileios Leon ◽  
Spyridon Mouselinos ◽  
Konstantina Koliogeorgi ◽  
Sotirios Xydis ◽  
Dimitrios Soudris ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Graphics Processing Unit ◽  
Inference Engine ◽  
Efficient Solutions ◽  
Processing Unit ◽  
Central Processing ◽  
Inference Engines ◽  
Field Programmable ◽  
Hardware Description

The workloads of Convolutional Neural Networks (CNNs) exhibit a streaming nature that makes them attractive for reconfigurable architectures such as the Field-Programmable Gate Arrays (FPGAs), while their increased need for low-power and speed has established Application-Specific Integrated Circuit (ASIC)-based accelerators as alternative efficient solutions. During the last five years, the development of Hardware Description Language (HDL)-based CNN accelerators, either for FPGA or ASIC, has seen huge academic interest due to their high-performance and room for optimizations. Towards this direction, we propose a library-based framework, which extends TensorFlow, the well-established machine learning framework, and automatically generates high-throughput CNN inference engines for FPGAs and ASICs. The framework allows software developers to exploit the benefits of FPGA/ASIC acceleration without requiring any expertise on HDL development and low-level design. Moreover, it provides a set of optimization knobs concerning the model architecture and the inference engine generation, allowing the developer to tune the accelerator according to the requirements of the respective use case. Our framework is evaluated by optimizing the LeNet CNN model on the MNIST dataset, and implementing FPGA- and ASIC-based accelerators using the generated inference engine. The optimal FPGA-based accelerator on Zynq-7000 delivers 93% less memory footprint and 54% less Look-Up Table (LUT) utilization, and up to 10× speedup on the inference execution vs. different Graphics Processing Unit (GPU) and Central Processing Unit (CPU) implementations of the same model, in exchange for a negligible accuracy loss, i.e., 0.89%. For the same accuracy drop, the 45 nm standard-cell-based ASIC accelerator provides an implementation which operates at 520 MHz and occupies an area of 0.059 mm 2 , while the power consumption is ∼7.5 mW.

Onboard Device Encapsulation With Two-Phase Cooling

2017 ◽  
Vol 10 (2) ◽  
Author(s):  
S. J. Young ◽  
D. Janssen ◽  
E. A. Wenzel ◽  
B. M. Shadakofsky ◽  
F. A. Kulacki
Keyword(s):  
Heat Transfer ◽  
Pressure Drop ◽  
Integrated Circuit ◽  
Flow Boiling ◽  
Heat Removal ◽  
Coolant Flow ◽  
Coefficient Of Performance ◽  
Processing Unit ◽  
Two Phase ◽  
Central Processing

Onboard liquid cooling of electronic devices is demonstrated with liquid delivered externally to the point of heat removal through a conformal encapsulation. The encapsulation creates a flat microgap above the integrated circuit (IC) and delivers a uniform inlet coolant flow over the device. The coolant is Novec™ 7200, and the electronics are simulated with a resistance heater on a 1:1 scale. Thermal performance is demonstrated at power densities of ∼1 kW/cm3 in the microgap. Parameters investigated are pressure drop, average device temperature, heat transfer coefficient, and coefficient of performance (COP). Nusselt numbers for gap sizes of 0.25, 0.5, and 0.75 mm are reduced to a dimensionless correlation. With low coolant inlet subcooling, two-phase heat transfer is seen at all mass flows. Device temperatures reach 95 °C for power dissipation of 50–80 W (0.67–1.08 kW/cm3) depending on coolant flow for a gap of 0.5 mm. Coefficients of performance of ∼100 to 70,000 are determined via measured pressure drop and demonstrate a low pumping penalty at the device level within the range of power and coolant flow considered. The encapsulation with microgap flow boiling provides a means for use of higher power central processing unit and graphics processing unit devices and thereby enables higher computing performance, for example, in embedded airborne computers.

Application of GPGPU to Accelerate CFD Simulation

2018 ◽  
Author(s):  
Shafiul A. Mintu ◽  
David Molyneux
Keyword(s):  
Cfd Simulation ◽  
Cost Benefit Analysis ◽  
Academic Research ◽  
Cost Effective ◽  
Surface Flow ◽  
Massively Parallel ◽  
Processing Unit ◽  
Regular Wave ◽  
Central Processing ◽  
Simulation Time

Computational Fluid Dynamics (CFD) is widely used in industry and academic research to investigate complex fluid flow. The bottleneck of a realistic CFD simulation is its long simulation time. The simulation time is generally reduced by massively parallel Central Processing Unit (CPU) clusters, which are very expensive. In this paper, it is shown that the CFD simulation can be accelerated significantly by a novel hardware called General Purpose Computing on Graphical Processing Units (GPGPU). GPGPU is a cost-effective computing cluster, which uses the Compute Unified Device Architecture (CUDA) of NVIDIA devices to transform the GPU into a massively parallel processor. The paper demonstrates the faster computing ability of GPU compared to a traditional multi-core CPU. Two scenarios are simulated; one is a 2-dimensional simulation of regular wave and another one is a 3-dimensional motion of a floating ship on a regular wave. A smoothed particle hydrodynamics (SPH) based CFD solver is used for simulating the complex free-surface flow. The performance of a single GPU is compared against a commonly used 16 core CPU. For a large simulation of 6 degrees of freedom (DOF) ship motion simulation, the comparative study exhibits a speedup of more than an order of magnitude, reducing simulation time from 30 hours to about 2 hours. This indicates a CUDA enabled GPU card can be used as a cost-effective computing tool for a reliable and accurate SPH-based CFD simulation. The cost-benefit analysis of GPU over a CPU cluster is also discussed.

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