scholarly journals Output Voltage Imbalance Compensation Using dc Offset Voltage for Split dc-Link Capacitor 3-Leg Inverter

Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 1029
Author(s):  
Sun-Pil Kim ◽  
Sung-Geun Song ◽  
Sung-Jun Park ◽  
Feel-soon Kang
Keyword(s):  
Output Voltage ◽  
Harmonic Distortion ◽  
Neutral Point ◽  
Total Harmonic Distortion ◽  
Phase 3 ◽  
Dc Offset ◽  
Phase Current ◽  
Compensation Algorithm ◽  
Offset Voltage ◽  
Circuit Structure

In this paper, we analyzed the output voltage imbalance and the cause of the offset voltage in 3-phase 3-leg inverters by using Millman’s theory. Based on this result, we proposed a voltage imbalance compensation algorithm using the dc offset voltage that appeared at the neutral point voltage of the load. To apply the proposed imbalance compensation algorithm, it needs a circuit structure of 3-phase 4-wire such as split dc-link capacitor 3-leg inverter and 4-leg inverter. Therefore, the total harmonic distortion (THD) of the load phase current according to the imbalance rate of the load was analyzed for the two inverters. Then, PSIM simulation and experiments based on a 10 kW-prototype of split dc-link capacitor 3-leg inverter were implemented to verify the validity of the proposed imbalance compensation algorithm.

scholarly journals Analysis of Symmetric and Asymmetric Multilevel Inverter Topologies Using Reduced Number of Switching Devices Circuit Structure

2018 ◽  
Vol 7 (4.30) ◽  
pp. 234
Author(s):  
M. H. Yatim ◽  
A. Ponniran ◽  
A. A. Bakar ◽  
A. N. Kasiran ◽  
K. R. Noor ◽  
...  
Keyword(s):  
Pulse Width ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Harmonic Distortion ◽  
Total Harmonic Distortion ◽  
Voltage Level ◽  
Switching Strategy ◽  
Circuit Structure ◽  
Sinusoidal Pulse Width Modulation ◽  
Switching Devices

This paper presents symmetric and asymmetric multilevel inverter principles using reduced number of switching devices circuit structure. Principally, asymmetric multilevel inverter topology able to produce higher output voltage level without modification of the structure in order to reduce total harmonic distortion at the output voltage. In contrast, the number of switching devices need to be increased with symmetric principle when higher output voltage level is considered. In this study, 5-level reduced number of switching devices circuit structure is selected as a circuit configuration for symmetric (5-level structure) and asymmetric (7-level and 9-level structures) multilevel inverters. For switching strategy, modified pulse width modulation and sinusoidal pulse width modulation are selected to produce output voltage levels of the inverter. Modified pulse width modulation used low switching frequency in producing signal and needs higher output voltage levels to achieve low total harmonic distortion. In contrast, sinusoidal pulse width modulation used high switching frequency in order to minimize total harmonic distortion. Theoretically, total harmonic distortion is reduced when number of output voltage level is increased for both cases. The findings show that, the 9-level asymmetric topology has lower total harmonic distortion compared to the 5-level symmetric topology and 7-level asymmetric topology, whereby these inverters using the same circuit configuration. The results show that, the total harmonic distortions of 9-level asymmetric topology, 7-level asymmetric topology and 5-level symmetric topology are 14.54%, 18.08% and 26.92%, respectively with sinusoidal pulse width modulation switching strategy. Meanwhile, with modified pulse width modulation switching strategy, the total harmonic distortions of 9-level asymmetric topology, 7-level asymmetric topology and 5-level symmetric topology are 18.7%, 21.68% and 28.99%, respectively. Therefore, 9-level asymmetric with sinusoidal pulse width modulation switching strategy show the lowest total harmonic distortion with optimum number of switching devices.

scholarly journals Multilevel inverter with MPWM-LFT switching strategy for voltage THD minimization

2019 ◽  
Vol 10 (3) ◽  
pp. 1461
Author(s):  
M. H. Yatim ◽  
A. Ponniran ◽  
A. N. Kasiran
Keyword(s):  
Pulse Width ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Harmonic Distortion ◽  
Multilevel Inverter ◽  
Total Harmonic Distortion ◽  
Switching Frequency ◽  
Switching Strategy ◽  
Circuit Structure ◽  
Switching Strategies

<span>This paper presents a proposed modified pulse width modulation – low frequency triangular (MPWM-LFT) switching strategy for minimization of voltage THD with implementation of asymmetric multilevel inverter (AMLI) topology on the reduced number of switching devices (RNSD) circuit structure. Principally, MPWM-LFT able to produce optimum angle of the output voltage level in order to minimize total harmonic distortion (THD). In this study, 5-level reduced number of switching devices circuit structure is selected as a circuit configuration for asymmetric (7-level structure) multilevel inverter. For switching strategy, MPWM used low switching frequency in producing signal and needs higher output voltage levels to achieve low total harmonic distortion. In contrast, sinusoidal pulse width modulation used high switching frequency in order to minimize total harmonic distortion. By optimizing angle at the output voltage using MPWM-LFT switching strategy, the voltage THD is lower as compared to MPWM and SPWM switching strategies. MPWM-LFT switching strategy obtains 11.6% of voltage THD for the 7-level asymmetric topology as compared to MPWM and SPWM switching strategies with the voltage THD are 21.5% and 17.5% respectively from the experimental works.</span>

scholarly journals DC Offset Error Compensation Algorithm for PR Current Control of a Single-Phase Grid-Tied Inverter

Energies ◽  
2018 ◽  
Vol 11 (9) ◽  
pp. 2308 ◽  
Author(s):  
Jae Lee ◽  
Seon-Hwan Hwang
Keyword(s):  
Fundamental Frequency ◽  
Error Compensation ◽  
Single Phase ◽  
Detection Method ◽  
Current Control ◽  
Dc Offset ◽  
Phase Current ◽  
Compensation Algorithm ◽  
Dc Component ◽  
Offset Error

In a single-phase grid-tied inverter, the direct current (DC) offset error included in the measured grid side phase current has various causes, such as a non-ideal current sensor, unbalanced power supply of an operational amplifier, and nonlinear features of analog components in interface circuits, etc. If the DC offset error is included in the measured current, it causes the secondary harmonic of fundamental frequency and the DC component in grid phase current which result in degradation of inverter performance. In this paper, a theoretical detection method of the secondary harmonic of the fundamental frequency and a DC component in grid phase current for a proportional-resonant (PR) current control system is introduced. Based on the detection method, an algorithm for compensating DC offset error is also presented for single-phase grid-tied inverters. Simulation results and experimental verification of the DC offset error compensation algorithm are shown in this paper.

scholarly journals Harmonics reduction of a five-level inverter by unbalanced carriers and over-modulation techniques

2018 ◽  
Vol 7 (3) ◽  
pp. 1059
Author(s):  
Mustafa Fawzi Mohammed ◽  
Ali Husain Ahmad ◽  
AbdulRahim Thiab Humod
Keyword(s):  
Fundamental Frequency ◽  
Output Voltage ◽  
Single Phase ◽  
Harmonic Distortion ◽  
Total Harmonic Distortion ◽  
Modulation Method ◽  
Labview Software ◽  
Design And Implementation ◽  
Modulation Techniques ◽  
Multi Level

The most concerns in the inverter's design are about, how to make the output voltage of the inverter sinusoidal at the desired fundamental frequency with low total harmonic distortion (THD). This paper presents a design and implementation of single-phase five-level inverter which is powered by single dc source and based on T-type multi-level inverters construction. The proposed inverter is built mainly by six IGBTs and two diodes. The used modulation technique is based on using two triangular carriers at 2000 Hz frequency and shifted by phase opposition disposition (POD) method. The carriers are made slightly unbalanced with their amplitudes. The over-modulation method is also introduced in the design to get the lowest possible THD effect without using filters. The inverter is simulated by MATLAB SIMULINK, implemented practically, and tested with the help of LabVIEW software.  

scholarly journals Multicarrier PWM Strategies for Hybrid Symmetrical Multilevel Inverter with Reduced Switch Count

2020 ◽  
Vol 9 (5) ◽  
pp. 860-866
Keyword(s):  
Electromagnetic Interference ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Harmonic Distortion ◽  
Multilevel Inverter ◽  
Total Harmonic Distortion ◽  
Switching Frequency ◽  
Third Harmonic ◽  
Multilevel Inverters ◽  
High Switching Frequency

Multilevel inverters are widely used for high power and high voltage applications. The performance of multilevel inverters are superior to conventional two level inverters in terms of reduced total harmonic distortion, higher dc link voltages, lower electromagnetic interference and increased quality in the output voltage waveform. This paper presents a single phase hybrid eleven level multilevel inverter topology with reduced switch count to compensate the above mentioned disadvantages. This paper also presents various high switching frequency based multi carrier pulse width modulation strategies such as Phase Disposition PWM Strategy (PDPWM), Phase Opposition and Disposition PWM Strategy (PODPWM), Alternate Phase opposition Disposition PWM (APODPWM), Carrier Overlapping PWM (COPWM), Variable frequency carrier PWM (VFPWM), Third Harmonic Injection PWM (TFIPWM) applied to the proposed eleven level multilevel inverter and is analyzed for RL load. FFT analysis is carried out and total harmonic distortion, fundamental output voltage are calculated. Simulation is carried out in MATLAB/SMULINK.

scholarly journals Circuit Structure and Control Method to Reduce Size and Harmonic Distortion of Interleaved Dual Buck Inverter

Energies ◽  
2020 ◽  
Vol 13 (6) ◽  
pp. 1531
Author(s):  
Min-Gi Cho ◽  
Sang-Hoon Lee ◽  
Hyeon-Seok Lee ◽  
Yoon-Geol Choi ◽  
Bongkoo Kang
Keyword(s):  
Output Power ◽  
High Power ◽  
Control Method ◽  
Power Conversion ◽  
Harmonic Distortion ◽  
Current Mode ◽  
Total Harmonic Distortion ◽  
Current Mode Control ◽  
Circuit Structure ◽  
And Control

A new circuit structure and control method for a high power interleaved dual-buck inverter are proposed. The proposed inverter consists of six switches, four diodes and two inductors, uses a dual-buck structure to eliminate zero-cross distortion, and operates in an interleaved mode to reduce the current stress of switch. To reduce the total harmonic distortion at low output power, the inverter is controlled using discontinuous-current-mode control combined with continuous-current-mode control. The experimental inverter had a power-conversion efficiency of 98.5% at output power = 1300 W and 98.3% at output power = 2 kW, when the inverter was operated at an input voltage of 400 VDC, output voltage of 220 VAC/60 Hz, and switching frequency of 20 kHz. The total harmonic distortion was < 0.66%, which demonstrates that the inverter is suitable for high-power dc-ac power conversion.

Enhanced frequency shift carrier modulation for H-bridge multilevel converter to conquer the impact of instability in deputize condenser voltage

2018 ◽  
Vol 57 (2) ◽  
pp. 164-174
Author(s):  
Yuvaraja T ◽  
KA Ramesh Kumar
Keyword(s):  
Frequency Shift ◽  
High Power ◽  
Output Voltage ◽  
Harmonic Distortion ◽  
Total Harmonic Distortion ◽  
Multilevel Converter ◽  
Control Scheme ◽  
Capacitor Voltage ◽  
Nonlinear Compensation ◽  
The Impact

H-bridge multilevel converter is the most challenging topology from nominal to high power applications. However, when the energy is exchanged between AC side and DC side or vice versa, the fluctuation in the capacitor used in deputize unit is unavoidable. The fluctuation in the deputize unit is due to the increase in the total harmonic distortion by the capacitor in the output voltages. This total harmonic distortion is evaded by exploring the deputize unit capacitor voltage mathematically. This paper proposes the enhanced frequency shift carrier modulation in H-bridge multilevel converter to suppress the influence of fluctuation in deputize unit capacitor voltages. Enhanced frequency shift carrier modulation is considered for nonlinear compensation. The principal results of using this enhanced frequency shift carrier modulation improvise the total harmonic distortion in the output voltage of H-bridge multilevel converter. Simulation and experimental results are done using MATLAB/SIMULINK to verify the effectiveness of the proposed control scheme.

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