scholarly journals MATRIX16: A 16-Channel Low-Power TDC ASIC with 8 ps Time Resolution

Electronics ◽  
2021 ◽  
Vol 10 (15) ◽  
pp. 1816
Author(s):  
Joan Mauricio ◽  
Lluís Freixas ◽  
Andreu Sanuy ◽  
Sergio Gómez ◽  
Rafel Manera ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Time Resolution ◽  
Time Of Flight ◽  
The Novel ◽  
Input Rate ◽  
Linearity Error ◽  
Supply Voltages ◽  
Novel Design

This paper presents a highly configurable 16-channel TDC ASIC designed in a commercial 180 nm technology with the following features: time-of-flight and time-over-threshold measurements, 8.6 ps LSB, 7.7 ps jitter, 5.6 ps linearity error, up to 5 MHz of sustained input rate per channel, 9.1 mW of power consumption per channel, and an area of 4.57 mm2. The main contributions of this work are the novel design of the clock interpolation circuitry based on a resistive interpolation mesh circuit and the capability to operate at different supply voltages and operating frequencies, thus providing a compromise between TDC resolution and power consumption.

A CMOS LOW-POWER TEMPERATURE-ROBUST RSSI USING WEAK-INVERSION LIMITING AMPLIFIERS

2013 ◽  
Vol 22 (10) ◽  
pp. 1340034 ◽  
Author(s):  
KEPING WANG ◽  
XUEMEI LEI ◽  
KAIXUE MA ◽  
KIAT SENG YEO ◽  
XIANG CAO ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Dynamic Range ◽  
Weak Inversion ◽  
Limiting Amplifier ◽  
Full Waveform ◽  
Transconductance Amplifier ◽  
Unique Nature ◽  
Low Power Cmos ◽  
Linearity Error

This paper presents a low-power CMOS receiving signal strength indicator (RSSI). The main architecture of the circuit adopts a six-stage limiting amplifier (LA) in a logarithmic-linear form, which shows a good performance in weak signal detection. The RSSI achieves high tolerance to process, voltage, and temperature (PVT) variations by utilizing the unique nature of branch currents in a transconductance amplifier. The power consumption is decreased by using the weak-inversion LAs. Full-waveform current rectification and summation are employed in the RSSI circuit to achieve high precision while maintaining low power consumption. Measured results show that in the 1 kHz–50 MHz frequency range, the input dynamic range is wider than 70 dB within ±2 dB linearity error. The chip occupies an area of 0.7 mm2 × 0.3 mm2 using a 0.18-μm CMOS. It draws 1.3 mA from a 1.8 V supply.

scholarly journals A Power Efficient Improved NOR-Type TCAM Design using OR-Type Match-Line Segment

2020 ◽  
Vol 8 (6) ◽  
pp. 4885-4890
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Performance ◽  
Cmos Technology ◽  
The Novel ◽  
Metal Gate ◽  
Power Efficient ◽  
Content Addressable Memory ◽  
Ternary Content Addressable Memory ◽  
High K

This paper presents the novel way to deal with diminish power utilization in a ternary content addressable memory (TCAM) designed in current innovation. The main aim of this TCAM design is to reduce the dynamic power consumption. In TCAM large amount of the power consumption happens during search operation, so we focussed on this area. Here right now give pragmatic plan of a TCAM which is arranged for low-power applications. Simulation of this design has done in Tanned EDA V.16 tool. For simulations of Low power TCAM designs we used predictive technology model (PTM) 45nm for high-performance applications which include metal gate, high-k and stress impact of CMOS technology.

Novel design of multiplexer and demultiplexer using reversible logic gates

2018 ◽  
Vol 7 (3.29) ◽  
pp. 80
Author(s):  
Veerendra Nath Nune ◽  
Addanki Purna R
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Logic Gates ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Gate Count ◽  
Reversible Logic Gates ◽  
Novel Design

Reversibility is the prominent technology in the recent era. In reversible logic the number output lines are equal to the number of input lines. In reversible logic the inputs are to be retrieved from the outputs. Reversible logic gates are user defined gates. Reversible logic owns its applications in various fields which include low power VLSI. In this paper multiplexer is implemented using QCA, SAM and QCA & SAM gate. Also demultiplexer is implemented using two new reversible logic gates RAMESH and RAMESH-1 gates. These designs are simulated and synthesized using Xilinx ISE 12.1 and Mentor Graphics tool. The result shows that the proposed designs are more efficient in terms of gate count, quantum cost and power consumption.  

scholarly journals Low Power Design of 2–4 and 4–16 Line Decoders

2019 ◽  
Vol 8 (9) ◽  
pp. 1220-1224
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Power Design ◽  
Low Power Consumption ◽  
Transmission Gate ◽  
Novel Design

Here, we are proposing a novel design of 2:4 decoder and 4:16 decoders which are designed by using line decoder concept. By using proposed design, the area and power consumption of 2:4 decoder and 4:16 decoder can be reduced. In the existing work they have used DVL (Dual Value Logic) and Transmission gate Logic to implement a 14-Transistor 2:4 decoder for minimizing the transistor count. By using 2:4 pre-decoders and post-decoders they implemented 4:16 decoders. Mixed logic is also used for this purpose. Here we have implemented a single 2:4 decoder with minimum transistor count and low power consumption which is used to design a 4:16 decoder. We implement the proposed design in Cadence Virtuoso simulation at 90nm technology and calculated the power and area.

scholarly journals Low Power Bidirectional Voltage Level Translator using Power Gating

2020 ◽  
Vol 9 (7) ◽  
pp. 977-981
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Gating ◽  
Voltage Level ◽  
Supply Voltages ◽  
Reduced Power Consumption ◽  
Multiple Supply Voltages

now a day’s, the demand for SoC based systems increasing. In SoC environment, multiple supply voltages are required because various subsystems of the system operate with different supply voltages. The communication between these systems is difficult and increases power consumption. The solution to this problem is to use a Voltage level translator/shifter between them. In this paper, a low power voltage level translator using power gating is proposed. By using this translator bidirectional voltage translator is implemented. In bidirectional voltage level translator, the data is translation between core logic and pad drivers and vice versa is possible with reduced power consumption and delay. In this paper, the power consumption reduces from 104uw to 6.25 pw at Vdd 1.8V. Delay is reduced from 19ns to 0.2 ns.

Optimal design of a high homogeneous and small-size shim coil for atomic spin gyroscope based on 0-1 linear programming

2020 ◽  
Vol 64 (1-4) ◽  
pp. 165-172
Author(s):  
Dongge Deng ◽  
Mingzhi Zhu ◽  
Qiang Shu ◽  
Baoxu Wang ◽  
Fei Yang
Keyword(s):  
Linear Programming ◽  
Power Consumption ◽  
Low Power ◽  
Optimization Design ◽  
Structural Parameters ◽  
Axial Position ◽  
Low Power Consumption ◽  
Optimal Method ◽  
Atomic Spin ◽  
Shim Coil

It is necessary to develop a high homogeneous, low power consumption, high frequency and small-size shim coil for high precision and low-cost atomic spin gyroscope (ASG). To provide the shim coil, a multi-objective optimization design method is proposed. All structural parameters including the wire diameter are optimized. In addition to the homogeneity, the size of optimized coil, especially the axial position and winding number, is restricted to develop the small-size shim coil with low power consumption. The 0-1 linear programming is adopted in the optimal model to conveniently describe winding distributions. The branch and bound algorithm is used to solve this model. Theoretical optimization results show that the homogeneity of the optimized shim coil is several orders of magnitudes better than the same-size solenoid. A simulation experiment is also conducted. Experimental results show that optimization results are verified, and power consumption of the optimized coil is about half of the solenoid when providing the same uniform magnetic field. This indicates that the proposed optimal method is feasible to develop shim coil for ASG.

An Ultra-low Power Consumption MAC Protocol Complied with IEEE 802.15.4/4e for Wireless Smart Utility Networks

2016 ◽  
Vol 136 (11) ◽  
pp. 1555-1566 ◽  
Author(s):  
Jun Fujiwara ◽  
Hiroshi Harada ◽  
Takuya Kawata ◽  
Kentaro Sakamoto ◽  
Sota Tsuchiya ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Ieee 802.15.4 ◽  
Mac Protocol ◽  
Low Power Consumption ◽  
Ultra Low Power
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