A 12-bit 1-MS/s 26-μW SAR ADC for Sensor Applications

2018 ◽  
Vol 3 (1) ◽  
Author(s):  
Yung-Hui Chung ◽  
Chia-Wei Yen ◽  
Cheng-Hsun Tsai
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Total Power ◽  
Measured Signal ◽  
Input Frequency ◽  
Dynamic Comparator ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Sensor Applications ◽  
Total Power Consumption

AbstractThis chapter presents an energy-efficient 12-bit 1-MS/s successive approximation register analog-to-digital converter (ADC) for sensor applications. A programmable dynamic comparator is proposed to suppress static current and maintain good linearity. A hybrid charge redistribution digital-to-analog converter is proposed to decrease the total capacitance, which would reduce the power consumption of the input and reference buffers. In the proposed ADC, its total input capacitance is only 700 fF, which greatly reduces the total power consumption of the analog frontend circuits. The 12-bit ADC is fabricated using 0.18-μm complementary metal-oxidesemiconductor technology, and it consumes only 26 μW from a 1 V supply at 1-MS/s. The measured signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 60.1 and 72.6 dB, respectively. The measured effective number of bits (ENOB) for a 100 kHz input frequency is 9.7 bits. At the Nyquist input frequency, the measured SNDR and SFDR are 59.7 and 71 dB, respectively. The ENOB is maintained at 9.6 bits and the figure-of-merit is 33.5 fJ/conversion-step.

Design of Low Power and High Precision Successive Approximation Register Analog-to-Digital Converter (SAR-ADC) Based on Piecewise Capacitance and Calibration Technique

2020 ◽  
Vol 15 (4) ◽  
pp. 478-486
Author(s):  
Sheng-Biao An ◽  
Li-Xin Zhao ◽  
Shi-Cong Yang ◽  
Tao An ◽  
Rui-Xia Yang
Keyword(s):  
Power Consumption ◽  
Successive Approximation ◽  
Dynamic Range ◽  
Sar Adc ◽  
Total Power ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Successive Approximation Register ◽  
Total Power Consumption

This paper presents a charge redistributed successive approximation register analog-to-digital converter (SAR ADC). Compared with the traditional Digital-Analog Convertor (DAC), the power consumption of the DAC scheme is reduced by 90%, the area is reduced by 60%. The test chip fabricated in 180 nm Complementary Metal Oxide Semiconductor (CMOS) occupied an active area of 0.12 mm 2 . At 10 MS/s, a signal-to-noise and distortion ratio (SNDR) of 57.70 dB and a spurious-free dynamic range (SFDR) of 55.63 dB are measured with 1.68 Vpp differential-mode input signal. The total power consumption is 690 μW corresponding to 67 fJ/conversion step figure of merit.

scholarly journals A Low Power Sigma-Delta Modulator with Hybrid Architecture

Sensors ◽  
2020 ◽  
Vol 20 (18) ◽  
pp. 5309
Author(s):  
Shengbiao An ◽  
Shuang Xia ◽  
Yue Ma ◽  
Arfan Ghani ◽  
Chan Hwang See ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Supply Voltage ◽  
Total Power ◽  
Cmos Process ◽  
Hybrid Architecture ◽  
Sigma Delta Modulator ◽  
Dynamic Comparator ◽  
Flash Adc ◽  
Total Power Consumption

Analogue-to-digital converters (ADC) using oversampling technology and the Σ-∆ modulation mechanism are widely applied in digital audio systems. This paper presents an audio modulator with high accuracy and low power consumption by using a discrete second-order feedforward structure. A 5-bit successive approximation register (SAR) quantizer is integrated into the chip, which reduces the number of comparators and the power consumption of the quantizer compared with flash ADC-type quantizers. An analogue passive adder is used to sum the input signals and it is embedded in a SAR ADC composed of a capacitor array and a dynamic comparator which has no static power consumption. To validate the design concept, the designed modulator is developed in a 180 nm CMOS process. The peak signal to noise distortion ratio (SNDR) is calculated as 106 dB and the total power consumption of the chip is recorded as 3.654 mW at the chip supply voltage of 1.8 V. The input sine wave of 0 to 25 kHz is sampled at a sampling frequency of 3.2 Ms/s. Moreover, the results achieve a 16-bit effective number of bits (ENOB) when the amplitude of the input signal is varied between 0.15 and 1.65 V. By comparing with other modulators which were realized by a 180 nm CMOS process, the proposed architecture outperforms with lower power consumption.

Design of a 10-Bit High Performance Current-Steering DAC with a Novel Nested Decoder Based on Domino Logic

2015 ◽  
Vol 24 (06) ◽  
pp. 1550086 ◽  
Author(s):  
Masoud Nazari ◽  
Leila Sharifi ◽  
Meysam Akbari ◽  
Omid Hashemipour
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Dynamic Range ◽  
Logic Gates ◽  
Cmos Technology ◽  
Total Power ◽  
Current Steering ◽  
Domino Logic ◽  
Chip Area ◽  
Total Power Consumption

In this paper, a 10-bit 8-2 segmented current-steering digital-to-analog converter (DAC) is presented which uses a novel nested binary to thermometer (BT) decoder based on domino logic gates. High accuracy and high performances are achieved with this structure. The proposed decoder has a pipelining scheme and it is designed symmetrically in three stages with repeatable logic gates. Thus, power consumption, chip area and the number of control signals are reduced. The proposed DAC is simulated in 0.18-μm CMOS technology and the spurious-free dynamic range (SFDR) is 65.3 dB over a 500 MHz output bandwidth at 1 GS/s. Total power consumption of the designed DAC is only 23.4 mW while the digital and analog supply voltages are 1.2 and 1.8 V, respectively. The active area of the proposed DAC is equal to 0.3 mm2.

A New Low Power Photoplethysmography Signal Acquisition System For Mental Stress Estimation

2021 ◽  
Author(s):  
Rajeev Kumar Pandey ◽  
Paul C.-P. Chao
Keyword(s):  
Standard Deviation ◽  
Power Consumption ◽  
Low Power ◽  
Dynamic Range ◽  
Acquisition System ◽  
Total Power ◽  
Signal Acquisition ◽  
Readout System ◽  
Pulse Rate Variability ◽  
Total Power Consumption

Abstract This study presents a new low power and robust reflectance type optical Photoplethysmography (PPG) acquisition system for the mental distress estimation. The front-end circuit is implemented in the integrated chip with chip area of 1200μm × 1200μm and fabricated via TSMC T18 process. The sensing range of the readout circuit is 20nA to 11μA, and the total power consumption of the readout system is 100μW. The total power consumption of the design chip including the OLED driver power is 1.64mW. The designed acquisition system is applied to the wrist artery of the two healthy patients when they are calculating the pictorial puzzles and when they are in relax state. The statistical deviation of the heart rate (HR) from the average HR is increased when subjects are in the stress. Also, the standard deviation of pulse rate variability (PRV), the dynamic range of pulse repetition time (PRT), and the standard deviation of PRV derivative show the increasing temporal value when subjects are in the stress.

A Capacitor-Splitting Switching Scheme with Low Total Power Consumption for SAR ADCs

2019 ◽  
Vol 28 (04) ◽  
pp. 1920002 ◽  
Author(s):  
Hao Wang ◽  
Wenming Xie ◽  
Zhixin Chen ◽  
Sijing Cai
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
Energy Efficient ◽  
Total Power ◽  
Switching Scheme ◽  
Analog To Digital ◽  
Switching Algorithm ◽  
Good Linearity ◽  
Total Power Consumption

A low-power capacitor-splitting switching algorithm for successive approximation register (SAR) and analog-to-digital converters (ADCs) is proposed. To reduce the total power consumption, it does not require reset energy, which accounts for a large proportion. Besides, energy-efficient one-side double-level switching technique is also utilized from the forth bit cycle. Thus, the proposed switching algorithm requires 26.54 CV[Formula: see text] total switching energy, 16.75% less over the tri-level one. Due to the capacitor-splitting structure, it also shows good linearity performance.

scholarly journals DESIGN OF A 500MHZ, 4-BIT LOW POWER ADC FOR UWB APPLICATION

2014 ◽  
pp. 81-86
Author(s):  
SANTOSH KUMAR PATNAIK ◽  
DR. SWAPNA BANERJEE
Keyword(s):  
Power Consumption ◽  
Input Signal ◽  
Power Supply ◽  
Cmos Technology ◽  
Sampling Frequency ◽  
Total Power ◽  
Digital Converter ◽  
Analog To Digital ◽  
Total Power Consumption ◽  
Single Power

This paper presents a new topology of an Analog-to-Digital Converter (ADC), named as Switched Reference ADC (SR-ADC) where the reference voltages are applied through switches. The switched reference voltage concept works with few mutually exclusive switches which are appropriately selecting the reference voltages for comparison with the input signal. This SR-ADC has been implemented using 0.18μm single poly and six metal CMOS technology. The spectra simulation result of this SR-ADC shows an ENOB of ≈3.53 for a 1V peak-to-peak input signal having a frequency of 100MHz while operating at a sampling frequency of 500MHz. The total power consumption is 21.39mW for a single power supply of 1.8V having a core area of ≈253μm*221μm.

scholarly journals A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

Sensors ◽  
2021 ◽  
Vol 21 (7) ◽  
pp. 2260
Author(s):  
Khuram Shehzad ◽  
Deeksha Verma ◽  
Danial Khan ◽  
Qurat Ul Ain ◽  
Muhammad Basim ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Intelligent Transportation System ◽  
Cmos Process ◽  
Process Technology ◽  
Back Issue ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Switching Method

A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.

scholarly journals Efficient Operation Method of Aquifer Thermal Energy Storage System Using Demand Response

Energies ◽  
2021 ◽  
Vol 14 (11) ◽  
pp. 3129
Author(s):  
Jewon Oh ◽  
Daisuke Sumiyoshi ◽  
Masatoshi Nishioka ◽  
Hyunbae Kim
Keyword(s):  
Energy Storage ◽  
Power Consumption ◽  
Thermal Energy ◽  
Demand Response ◽  
Thermal Energy Storage ◽  
Heat Storage ◽  
Storage System ◽  
Total Power ◽  
Operation Method ◽  
Total Power Consumption

The mass introduction of renewable energy is essential to reduce carbon dioxide emissions. We examined an operation method that combines the surplus energy of photovoltaic power generation using demand response (DR), which recognizes the balance between power supply and demand, with an aquifer heat storage system. In the case that predicts the occurrence of DR and performs DR storage and heat dissipation operation, the result was an operation that can suppress daytime power consumption without increasing total power consumption. Case 1-2, which performs nighttime heat storage operation for about 6 h, has become an operation that suppresses daytime power consumption by more than 60%. Furthermore, the increase in total power consumption was suppressed by combining DR heat storage operation. The long night heat storage operation did not use up the heat storage amount. Therefore, it is recommended to the heat storage operation at night as much as possible before DR occurs. In the target area of this study, the underground temperature was 19.1 °C, the room temperature during cooling was about 25 °C and groundwater could be used as the heat source. The aquifer thermal energy storage (ATES) system in this study uses three wells, and consists of a well that pumps groundwater, a heat storage well that stores heat and a well that used heat and then returns it. Care must be taken using such an operation method depending on the layer configuration.

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