scholarly journals Metamaterial-Engineered Silicon Beam Splitter Fabricated with Deep UV Immersion Lithography

Nanomaterials ◽  
2021 ◽  
Vol 11 (11) ◽  
pp. 2949
Author(s):  
Vladyslav Vakarin ◽  
Daniele Melati ◽  
Thi Thuy Duong Dinh ◽  
Xavier Le Roux ◽  
Warren Kut King Kan ◽  
...  
Keyword(s):  
High Performance ◽  
Design Space ◽  
Beam Splitter ◽  
High Volume ◽  
Silicon On Insulator ◽  
Feature Size ◽  
Immersion Lithography ◽  
Propagation Of Light ◽  
Silicon Photonic ◽  
Deep Ultraviolet

Subwavelength grating (SWG) metamaterials have garnered a great interest for their singular capability to shape the material properties and the propagation of light, allowing the realization of devices with unprecedented performance. However, practical SWG implementations are limited by fabrication constraints, such as minimum feature size, that restrict the available design space or compromise compatibility with high-volume fabrication technologies. Indeed, most successful SWG realizations so far relied on electron-beam lithographic techniques, compromising the scalability of the approach. Here, we report the experimental demonstration of an SWG metamaterial engineered beam splitter fabricated with deep-ultraviolet immersion lithography in a 300-mm silicon-on-insulator technology. The metamaterial beam splitter exhibits high performance over a measured bandwidth exceeding 186 nm centered at 1550 nm. These results open a new route for the development of scalable silicon photonic circuits exploiting flexible metamaterial engineering.

Research of High Performance Polarization-Independent Grating Beam Splitter

2013 ◽  
Vol 310 ◽  
pp. 481-485
Author(s):  
Ke Zhao ◽  
Xiao Min Lei ◽  
Guo Feng Xie ◽  
Wen Hua Xiong
Keyword(s):  
High Performance ◽  
Beam Splitter ◽  
Transverse Electric ◽  
Transverse Magnetic ◽  
Silicon On Insulator ◽  
Material System ◽  
Design And Optimization ◽  
Rigorous Coupled Wave Analysis ◽  
Rigorous Coupled Wave ◽  
Polarization Independent

Based on a silicon-on-insulator (Silicon-on-insulator, SOI) material system design and optimization of a high performance, the polarization independent of 1 × 3 subwavelength grating stars beam splitter. By a rigorous coupled-wave analysis method showed that, in the 1550nm wavelength range, at vertical incidence, the device on the transverse electric field (transverse electric, TE) ,the 0 and ± 1 order transmittance is 31%, 32%, 32%,respectively; cross the magnetic field (transverse magnetic, TM), the 0 and ± 1 transmittance is 33%, 32%, 32%, respectively.

193nm immersion lithography for high-performance silicon photonic circuits

2014 ◽  
Author(s):  
Shankar K. Selvaraja ◽  
Gustaf Winroth ◽  
Sabrina Locorotondo ◽  
Gayle Murdoch ◽  
Alexey Milenin ◽  
...  
Keyword(s):  
High Performance ◽  
Photonic Circuits ◽  
Immersion Lithography ◽  
Silicon Photonic

scholarly journals Evaluation of Static Mapping for Dynamic Space-Shared Multi-task Processing on FPGAs

2021 ◽  
Author(s):  
Umar Ibrahim Minhas ◽  
Roger Woods ◽  
Georgios Karakonstantis
Keyword(s):  
High Performance ◽  
Design Space Exploration ◽  
Design Space ◽  
System Throughput ◽  
Design Parameters ◽  
Temporal Constraints ◽  
Shared Resources ◽  
Task Processing ◽  
High Level ◽  
Performance Computing

AbstractWhilst FPGAs have been used in cloud ecosystems, it is still extremely challenging to achieve high compute density when mapping heterogeneous multi-tasks on shared resources at runtime. This work addresses this by treating the FPGA resource as a service and employing multi-task processing at the high level, design space exploration and static off-line partitioning in order to allow more efficient mapping of heterogeneous tasks onto the FPGA. In addition, a new, comprehensive runtime functional simulator is used to evaluate the effect of various spatial and temporal constraints on both the existing and new approaches when varying system design parameters. A comprehensive suite of real high performance computing tasks was implemented on a Nallatech 385 FPGA card and show that our approach can provide on average 2.9 × and 2.3 × higher system throughput for compute and mixed intensity tasks, while 0.2 × lower for memory intensive tasks due to external memory access latency and bandwidth limitations. The work has been extended by introducing a novel scheduling scheme to enhance temporal utilization of resources when using the proposed approach. Additional results for large queues of mixed intensity tasks (compute and memory) show that the proposed partitioning and scheduling approach can provide higher than 3 × system speedup over previous schemes.

scholarly journals Core-Level Modeling and Frequency Prediction for DSP Applications on FPGAs

2015 ◽  
Vol 2015 ◽  
pp. 1-20
Author(s):  
Gongyu Wang ◽  
Greg Stitt ◽  
Herman Lam ◽  
Alan George
Keyword(s):  
High Performance ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Core Level ◽  
Prediction Methods ◽  
Clock Frequency ◽  
Worst Case ◽  
Model Based ◽  
Dsp Applications

Field-programmable gate arrays (FPGAs) provide a promising technology that can improve performance of many high-performance computing and embedded applications. However, unlike software design tools, the relatively immature state of FPGA tools significantly limits productivity and consequently prevents widespread adoption of the technology. For example, the lengthy design-translate-execute (DTE) process often must be iterated to meet the application requirements. Previous works have enabled model-based, design-space exploration to reduce DTE iterations but are limited by a lack of accurate model-based prediction of key design parameters, the most important of which is clock frequency. In this paper, we present a core-level modeling and design (CMD) methodology that enables modeling of FPGA applications at an abstract level and yet produces accurate predictions of parameters such as clock frequency, resource utilization (i.e., area), and latency. We evaluate CMD’s prediction methods using several high-performance DSP applications on various families of FPGAs and show an average clock-frequency prediction error of 3.6%, with a worst-case error of 20.4%, compared to the best of existing high-level prediction methods, 13.9% average error with 48.2% worst-case error. We also demonstrate how such prediction enables accurate design-space exploration without coding in a hardware-description language (HDL), significantly reducing the total design time.

Recent Progress in SOI Materials and Devices for VLSI Applications

1993 ◽  
Vol 316 ◽  
Author(s):  
H. H. Hosack
Keyword(s):  
High Performance ◽  
Large Scale ◽  
Recent Progress ◽  
Low Voltage ◽  
Silicon On Insulator ◽  
Significant Interest ◽  
Significant Performance ◽  
Cmos Ic ◽  
Bulk Processing ◽  
Soi Technology

Silicon-On-Insulator (SOI) technology [1-4] has been shown to have significant performance and fabrication advantages over conventional bulk processing for a wide variety of large scale CMOS IC applications. Advantages in radiation environments has generated significant interest in this technology from military and space science communities [5,6]. Possible advantages of SOI technology for low power, low voltage and high performance circuit applications is under serious consideration by several commercial IC manufacturers [7,8].

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