scholarly journals Analysis and Design of a CMOS Ultra-High-Speed Burst Mode Imager with In-Situ Storage Topology Featuring In-Pixel CDS Amplification

Sensors ◽  
2018 ◽  
Vol 18 (11) ◽  
pp. 3683
Author(s):  
Linkun Wu ◽  
David San Segundo Bello ◽  
Philippe Coppejans ◽  
Jan Craninckx ◽  
Andreas Süss ◽  
...  

This paper presents an in-situ storage topology for ultra-high-speed burst mode imagers, enabling low noise operation while keeping a high frame depth. The proposed pixel architecture contains a 4T pinned photodiode, a correlated double sampling (CDS) amplification stage, and an in-situ memory bank. Focusing on the sampling noise, the system level trade-off of the proposed pixel architecture is discussed, showing its advantages on the noise, power, and scaling capability. Integrated with an AC coupling CDS stage, the amplification is obtained by exploiting the strong capacitance to the voltage relation of a single NMOS transistor. A comprehensive noise model is developed for optimizing the trade-off between the area and noise. As a proof-of-concept, a prototype imager with a 30 µm pixel pitch was fabricated in a CMOS 130 nm technology. A 108-cell memory bank is implemented allowing dense layout and parallel readout. Two types of CDS amplification stages were investigated. Despite the limited memory capacitance of 10 fF/cell, the photon transfer curves of both pixel types were measured over different operation speeds up to 20 Mfps showing a noise performance of 8.4 e−.

2021 ◽  
Vol 129 (18) ◽  
pp. 183305
Author(s):  
Mário Janda ◽  
Mostafa E. Hassan ◽  
Viktor Martišovitš ◽  
Karol Hensel ◽  
Michal Kwiatkowski ◽  
...  

2013 ◽  
Vol 712-715 ◽  
pp. 1771-1774
Author(s):  
Ey Goo Kang

Power MOSFET is develop in power savings, high efficiency, small size, high reliability, fast switching, low noise. Power MOSFET can be used high-speed switching transistors devices. Recently attention to the motor and the application of various technologies. Power MOSFET is devices the voltage-driven approach switching devices are design to handle on large power, power supplies, converters, motor controllers. In this paper, design the 400 V Planar type, and design the trench type for realization of low on-resistance. Trench Power MOSFET Vth : 3.25 V BV : 484 V Ron : 0.0395 Ohm has been optimized.


2011 ◽  
Vol 9 ◽  
pp. 219-223
Author(s):  
S. Lange ◽  
T. Reich ◽  
J. Nowak ◽  
B. Dimov ◽  
M. Meister ◽  
...  

Abstract. A high-speed photo detector IC for application in Blu-ray/DVD/CD drives is presented. Bandwidths for the highest gain of 254 MHz and 221 MHz for 405 nm (Blu-ray) and 635 nm (DVD) wavelengths, respectively, were achieved by applying novel design methodologies. The combination of this outstanding speed performance with its low power dissipation of 192 mW at 5V supply and the low noise power of −72 dBm at 300 MHz makes it the best in literature reported optical transceiver IC for Blu-ray and Blu-ray/DVD/CD multi drives. Beside the excellent performance results, the usage of the novel design methodologies gave us an increased design efficiency with 25% compared to earlier similar design processes.


2006 ◽  
Vol 19 (5) ◽  
pp. S235-S241 ◽  
Author(s):  
Dietmar Drung ◽  
Colmar Hinnrichs ◽  
Henry-Jobes Barthelmess

2012 ◽  
Vol 21 (06) ◽  
pp. 1240011 ◽  
Author(s):  
JANGJOON LEE ◽  
SRIKAR BHAGAVATULA ◽  
SWARUP BHUNIA ◽  
KAUSHIK ROY ◽  
BYUNGHOO JUNG

CMOS technologies are suffering from increased variability due to process, supply voltage and temperature (PVT) variations as we enter the tens-of-nanometer regime. Analog and mixed-signal circuits have failed to effectively exploit the high-speed and low-noise properties that deep scaled CMOS technologies provide due to marginality issues. Large variations in leakage current and threshold voltage also make highly integrated digital designs challenging. In addition, device aging introduces a temporal dimension to variations in circuit performance. Consequently, there is an increasing need for a new design methodology that can provide high yield and reliability under severe parametric variations. Although several post-silicon calibration and repair strategies have been proposed to address the PVT variations, no coherent design strategy for a SoC has been developed so far. We espouse a self-healing technique based on real-time sensing and built-in feedback due to its inherent advantage of dynamic adaptation to temporal variations. This tutorial paper outlines our vision of improving marginalities in deep scaled CMOS technologies using a generic and systematic self-healing design including a system-level auto-correction algorithm. It also illustrates this methodology with design examples.


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