scholarly journals A Proficient Performance Scrutiny of King Mesh Topology based on the Routing Algorithms

2019 ◽  
Vol 8 (9) ◽  
pp. 3148-3153
Keyword(s):  
System Performance ◽  
Associate Degree ◽  
Network On Chip ◽  
Routing Algorithms ◽  
Path Selection ◽  
System On Chip ◽  
Long Distance ◽  
Mesh Topology ◽  
Routing Techniques ◽  
On Chip

Network on Chip (NoC), is an associate degree approach to construct the interaction between subsystems. The number of cores in a System on Chip (SoC) increases gradually in the pre-decades and affect the system performance. The scalability of SoC is improved by NoC architectures where topology contains an important impact on the performance and cost of the network. Mesh, Torus is some of the topologies used in NoC system design. King mesh topology is the concept introduced to improve the performance of the NoC system. King topology introduces some new advancement in the performance of mesh and torus topology. The king mesh topology provides number of advantages such as reduced execution time in parallel processing applications. In king mesh topology the transmission latency of long distance traffic is high. The proposed XY routing and Weight based Path Selection (WPS) routing techniques increases the speed of the system, reduce the area utilization and power consumption and reduce the number of hop counts by finding the shortest path

Comparative Performance Analysis of 
Selected Routing Algorithms by Load Variation of 2-Dimensional Mesh Topology Based 
Network-On-Chip

2021 ◽  
Vol 20 (3) ◽  
pp. 1-6
Author(s):  
Mohammed Shaba Saliu ◽  
Muyideen Omuya Momoh ◽  
Pascal Uchenna Chinedu ◽  
Wilson Nwankwo ◽  
Aliu Daniel
Keyword(s):  
Routing Algorithm ◽  
Adaptive Routing ◽  
Injection Rate ◽  
Network On Chip ◽  
Routing Algorithms ◽  
Comparative Performance ◽  
Traffic Pattern ◽  
Mesh Topology ◽  
Similar Vein ◽  
On Chip

Network-on-Chip (NoC) has been proposed as a viable solution to the communication challenges on System-on-Chips (SoCs). As the communication paradigm of SoC, NoCs performance depends mainly on the type of routing algorithm chosen. In this paper different categories of routing algorithms were compared. These include XY routing, OE turn model adaptive routing, DyAD routing and Age-Aware adaptive routing.  By varying the load at different Packet Injection Rate (PIR) under random traffic pattern, comparison was conducted using a 4 × 4 mesh topology. The Noxim simulator, a cycle accurate systemC based simulator was employed. The packets were modeled as a Poisson distribution; first-in-first-out (FIFO) input buffer channel with a depth of five (5) flits and a flit size of 32 bits; and a packet size of 3 flits respectively. The simulation time was 10,000 cycles. The findings showed that the XY routing algorithm performed better when the PIR is low.  In a similar vein, the DyAD routing and Age-aware algorithms performed better when the load i.e. PIR is high.

scholarly journals Congestion-Aware Routing Algorithm for NoC Using Data Packets

2021 ◽  
Vol 2021 ◽  
pp. 1-11
Author(s):  
Khurshid Ahmad ◽  
Muhammad Athar Javed Sethi ◽  
Rehmat Ullah ◽  
Imran Ahmed ◽  
Amjad Ullah ◽  
...  
Keyword(s):  
Routing Algorithm ◽  
Network On Chip ◽  
Routing Algorithms ◽  
System On Chip ◽  
Multiprocessor System ◽  
Data Packets ◽  
Communication Framework ◽  
Using Data ◽  
On Chip ◽  
Congestion Aware

Network on Chip (NoC) is a communication framework for the Multiprocessor System on Chip (MPSoC). It is a router-based communication system. In NoC architecture, nodes of MPSoC are communicating through the network. Different routing algorithms have been developed by researchers, e.g., XY, intermittent XY, DyAD, and DyXY. The main problems in these algorithms are congestion and faults. Congestion and faults cause delay, which degrades the performance of NoC. A congestion-aware algorithm is used for the distribution of traffic over NoC and for the avoidance of congestion. In this paper, a congestion-aware routing algorithm is proposed. The algorithm works by sending congestion information in the data packet. The algorithm is implemented on a 4 × 4 mesh NoC using FPGA. The proposed algorithm decreases latency, increases throughput, and uses less bandwidth in sharing congestion information between routers in comparison to the existing congestion-aware routing algorithms.

Macro and Micro Architectures for Network on Chip

2021 ◽  
pp. 44-74
Author(s):  
P. Suresh
Keyword(s):  
Computer Network ◽  
Network On Chip ◽  
Routing Algorithms ◽  
System On Chip ◽  
System Level ◽  
Comparison Result ◽  
New Concepts ◽  
Different Dimensions ◽  
Mesh Architecture ◽  
On Chip

Network on chip (NoC) paradigm replaces traditional, dedicated, and proprietary bus architectures of system on chip (SoC), and it is widely accepted by the system-level designers. In this chapter, an overview of the NoC design is presented in two different dimensions called macro-architectures and micro-architectures based on the design perspectives. Macro-architectures adopt the concept of computer network along with new innovations in topologies, protocols, and routing algorithms and so on whereas micro-architectures involve in the development of schedulers, arbiters, routers, and network adapter with existing or new concepts. From the comparison result, most of the NoC prototypes are developed with 2-D mesh architecture with packed switched concept. Apart from mesh architectures, some of the complex and hybrid concepts are also developed and discussed in this chapter.

YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAs

2019 ◽  
Vol 28 (12) ◽  
pp. 1950202 ◽  
Author(s):  
Khyamling Parane ◽  
B. M. Prabhu Prasad ◽  
Basavaraj Talawar
Keyword(s):  
Design Space Exploration ◽  
Routing Algorithm ◽  
Adaptive Routing ◽  
Network On Chip ◽  
Routing Algorithms ◽  
Tree Topology ◽  
Traffic Pattern ◽  
Mesh Topology ◽  
On Chip ◽  
Congestion Aware

Many-core systems employ the Network on Chip (NoC) as the underlying communication architecture. To achieve an optimized design for an application under consideration, there is a need for fast and flexible NoC simulator. This paper presents an FPGA-based NoC simulation acceleration framework supporting design space exploration of standard and custom NoC topologies considering a full set of microarchitectural parameters. The framework is capable of designing custom routing algorithms, various traffic patterns such as uniform random, transpose, bit complement and random permutation are supported. For conventional NoCs, the standard minimal routing algorithms are supported. For designing the custom topologies, the table-based routing has been implemented. A custom topology called diagonal mesh has been evaluated using table-based and novel shortest path routing algorithm. A congestion-aware adaptive routing has been proposed to route the packets along the minimally congested path. The congestion-aware adaptive routing algorithm has negligible FPGA area overhead compared to the conventional XY routing. Employing the congestion-aware adaptive routing, network latency is reduced by 55% compared to the XY routing algorithm. The microarchitectural parameters such as buffer depth, traffic pattern and flit width have been varied to observe the effect on NoC behavior. For the [Formula: see text] mesh topology, the LUT and FF usages will be increased from 32.23% to 34.45% and from 12.62% to 15% considering the buffer depth of 4 and flit widths of 16 bits, and 32 bits, respectively. Similar behavior has been observed for other configurations of buffer depth and flit width. The torus topology consumes 24% more resources than the mesh topology. The 56-node fat tree topology consumes 27% and 2.2% more FPGA resources than the [Formula: see text] mesh and torus topologies. The 56-node fat tree topology with buffer depth of 8 and 16 flits saturates at the injection rates of 40% and 45%, respectively.

scholarly journals Throughput Enhancement of Continuous Time Replication Strategy using Multicast GALS in NoCs

2020 ◽  
Vol 9 (5) ◽  
pp. 1085-1090
Keyword(s):  
Network On Chip ◽  
System On Chip ◽  
Single Chip ◽  
Data Packets ◽  
Mesh Topology ◽  
Modern Development ◽  
Asynchronous Transmission ◽  
On Chip ◽  
The Impact ◽  
Parallel Communication

The network-on-Chip (NoC) design is the modern development in communication as the integration of the multiple network blocks in a single chip. Before the NoC, system on chip (SoC) was implemented. Development in the day to day the features were added to overcome the SoC like potential of the system on chip, operation frequencies, wiring congestion and size of the chip etc., as the SoC has the long sensitive path which shows the impact on the size of the chip. In wiring congestion: Routing a particular data with SoC requires lot of wirings. Coming to the NoC also developed in packet transferring from source to destination. Serial communication were first used to transfer as it take much time to transfer the data packets from the source to destination to overcome the serial path communication, parallel communication is used. In Parallel communication the packets are transferred from source to destination at a time. To improve the packet transfer in network many techniques are used like mesh topology, tree topology etc. The existing system will supports only the mesh topology and one to many packet transfer. In the proposed system, the new parallel multicast which uses the Globally Asynchronous and locally Synchronous Network on Chip (GALS NoC) that includes both Synchronous and Asynchronous Transmission with a slight change in IPM and OPM Architecture to support both synchronous and asynchronous transmission and reception of data packets. It has several advantages like it supports efficient many-to-one traffic, it is suitable for any topology and has improved Throughput.

Design of Router Supporting Multiply Routing Algorithm for NoC

2014 ◽  
Vol 981 ◽  
pp. 431-434
Author(s):  
Zhan Peng Jiang ◽  
Rui Xu ◽  
Chang Chun Dong ◽  
Lin Hai Cui
Keyword(s):  
Complex System ◽  
High Performance ◽  
Routing Algorithm ◽  
Network On Chip ◽  
System On Chip ◽  
Low Latency ◽  
Deterministic Routing ◽  
Key Features ◽  
Design Challenge ◽  
On Chip

Network on Chip(NoC)，a new proposed solution to solve global communication problem in complex System on Chip (SoC) design，has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus，and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

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