scholarly journals Integer N Synthesizer Design for LoRa Transceivers

2021 ◽  
Vol 10 (10) ◽  
pp. 101-106
Author(s):  
Vitor Fialho* ◽  
Keyword(s):  
Steady State ◽  
Charge Pump ◽  
Settling Time ◽  
Loop Filter ◽  
Steady State Analysis ◽  
Phase Frequency Detector ◽  
Voltage Controlled Oscillators ◽  
Frequency Detector ◽  
State Analysis

This paper presents the study and design of an Integer N synthesizer model for three LoRa ISM bands: 430 MHz 868 MHz and 915 MHz. The proposed topology is composed by two voltage controlled oscillators working in two different bands. The presented model uses the same phase-frequency detector, charge pump and loop filter. This study is focused on dynamic and steady-state analysis in order to infer the synthesizer stability and bandwidth. The performed study shows that the settling time for all bands is less than 40 µs for a bandwidth of 102 kHz.

Analysis and Design of High Performance Phase Frequency Detector, Charge Pump and Loop Filter Circuits for Phase Locked Loop in Wireless Applications

2016 ◽  
Vol 4 (2) ◽  
pp. 397
Author(s):  
P.N. Metange ◽  
K. B. Khanchandani
Keyword(s):  
Leakage Current ◽  
High Performance ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Loop Filter ◽  
Phase Frequency Detector ◽  
Analysis And Design ◽  
Wireless Applications ◽  
5 Ghz ◽  
Frequency Detector

<p>This paper presents the analysis and design of high performance phase frequency detector, charge pump and loop filter circuits for phase locked loop in wireless applications. The proposed phase frequency detector (PFD) consumes only 8 µW and utilises small area. Also, at 1.8V voltage supply the maximum operation frequency of the conventional PFD is 500 MHz whereas proposed PFD is 5 GHz. Hence, highly suitable for low power, high speed and low jitter applications.  The differential charge pump uses switches using NMOS and the inverter delays for up and down signals do not generate any offset due to its fully symmetric operation. This configuration doubles the range of output voltage compliance compared to single ended charge pump. Differential stage is less sensitive to the leakage current since leakage current behaves as common mode offset with the dual output stages. All the circuits are implemented using cadence 0.18 μm CMOS Process.</p>

A LOW-VOLTAGE LOW-POWER CMOS PHASE-LOCKED LOOP

2005 ◽  
Vol 14 (05) ◽  
pp. 997-1006 ◽  
Author(s):  
ROBERT C. CHANG ◽  
LUNG-CHIH KUO ◽  
HOU-MING CHEN
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Loop Filter ◽  
Phase Frequency Detector ◽  
Low Power Cmos ◽  
Charge Pump Circuit ◽  
Frequency Detector

A low-voltage low-power CMOS phase-locked loop (PLL) is presented in this paper. It consists of a phase frequency detector, a charge pump, a loop filter, a voltage-control oscillator, and a frequency divider. A new phase frequency detector is proposed to reduce the dead zone and the mismatch effect of the charge pump circuit. A novel charge pump circuit with a small area and wide output range is described. The PLL circuit has been designed using the TSMC 0.35 μm 1P4M CMOS technology. The chip area is 1.08 mm × 1.01 mm. The post-layout simulation results show that the frequency of 900 MHz can be generated with a single supply voltage of 1.5 V. The power dissipation of the circuit is 9.17 mW.

Analysis of Single Buffer Random Polling System With State-Dependent Input Process and Server/Station Breakdowns

2018 ◽  
Vol 9 (1) ◽  
pp. 22-50 ◽  
Author(s):  
Thomas Y.S. Lee
Keyword(s):  
Steady State ◽  
Linear Model ◽  
Repair Process ◽  
Polling System ◽  
Steady State Analysis ◽  
Relaxation System ◽  
Polling Model ◽  
State Dependent ◽  
Non Linear ◽  
State Analysis

Models and analytical techniques are developed to evaluate the performance of two variations of single buffers (conventional and buffer relaxation system) multiple queues system. In the conventional system, each queue can have at most one customer at any time and newly arriving customers find the buffer full are lost. In the buffer relaxation system, the queue being served may have two customers, while each of the other queues may have at most one customer. Thomas Y.S. Lee developed a state-dependent non-linear model of uncertainty for analyzing a random polling system with server breakdown/repair, multi-phase service, correlated input processes, and single buffers. The state-dependent non-linear model of uncertainty introduced in this paper allows us to incorporate correlated arrival processes where the customer arrival rate depends on the location of the server and/or the server's mode of operation into the polling model. The author allows the possibility that the server is unreliable. Specifically, when the server visits a queue, Lee assumes that the system is subject to two types of failures: queue-dependent, and general. General failures are observed upon server arrival at a queue. But there are two possibilities that a queue-dependent breakdown (if occurs) can be observed; (i) is observed immediately when it occurs and (ii) is observed only at the end of the current service. In both cases, a repair process is initiated immediately after the queue-dependent breakdown is observed. The author's model allows the possibility of the server breakdowns/repair process to be non-stationary in the number of breakdowns/repairs to reflect that breakdowns/repairs or customer processing may be progressively easier or harder, or that they follow a more general learning curve. Thomas Y.S. Lee will show that his model encompasses a variety of examples. He was able to perform both transient and steady state analysis. The steady state analysis allows us to compute several performance measures including the average customer waiting time, loss probability, throughput and mean cycle time.

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