scholarly journals Dynamic VlSI Methods for OLSE and Syndrome Calculation using Synchronized Mitigation Procedures for Intact Circuit Functionality

2019 ◽  
Vol 8 (2S4) ◽  
pp. 383-386
Keyword(s):  
Error Correction ◽  
Research Work ◽  
Vlsi Design ◽  
Error Correction Codes ◽  
Electronic Circuits ◽  
Verilog Hdl ◽  
Suggested Technique ◽  
Major Parameter ◽  
Decoder Circuit

Now a days in VLSI design circuit’s reliability has become the major parameter of concern. With the consistently expanding requests for higher speed and lower control correspondence frameworks, productive VLSI executions of those blunder redress codes have extraordinary significance for reasonable applications. There exists various synchronized moderation procedures proposed to ensure that the blunders don't influence the circuit usefulness. Among them, to ensure the recollections and registers in electronic circuits Error Correction Codes (ECC) is normally utilized. At whatever point any ECC method is utilized, the encoder and decoder circuit may likewise endure mistakes. Here synchronized slip identification Also revision method to OLS encoders (OLSE) What's more syndrome figuring is suggested What's more assessed. Those suggested technique proficiently executes An equality prediction plan that detects the greater part errors that influence An solitary out hub utilizing the properties of OLS codes. Today VLSI design means usage of Verilog or VHDL. In this research work Verilog HDL is used for simulation and Synplify for synthesis purpose.

scholarly journals Design of low- area, power fault tolerant parallel FFTs using trellis codes

2018 ◽  
Vol 7 (4) ◽  
pp. 2338
Author(s):  
B. NagaSaiLakshmi ◽  
RajaSekhar. T
Keyword(s):  
Error Correction ◽  
Fault Tolerant ◽  
Error Correction Codes ◽  
Electronic Circuits ◽  
Trellis Codes ◽  
Low Area ◽  
Trellis Code ◽  
Synthesis Report ◽  
Parallel Fft ◽  
Algorithmic Based Fault Tolerance

Present day electronic circuits are generally affected by the delicate mistakes. To maintain the reliability of the complex systems few techniques have been proposed. For few applications, an algorithmic - based fault tolerance (ABFT) system has attempt to abuse the algorithmic properties to identify and adjust mistakes. One example FFT used. There are various protection schemes to identify and adjust errors in FFTs. It is normal to discover various blocks are working in parallel. Recently; a new method is exploiting to implement a blame tolerance in parallel. In this work, same method is first applicable to parallel FFT and then secured methods are merged that the use of error correction codes (ECCs) and parseval checks are used to detect and correct a single bit fault. Trellis code is applied to parallel FFTs to protect the errors which are used to detect and correct a multibit faults are proposed and evaluated. The 4-point FFT is protected with the input32-bit length .Simulation and Synthesis report for FFT using ECC,SOS,ECC-SOS,Trellis codes are obtained in Xilinx software14.2v.Area,power,delay is analyzed in cadence using 90nm & 180nmTechnology. 

scholarly journals Deep PUF: A Highly Reliable DRAM PUF-Based Authentication for IoT Networks Using Deep Convolutional Neural Networks

Sensors ◽  
2021 ◽  
Vol 21 (6) ◽  
pp. 2009
Author(s):  
Fatemeh Najafi ◽  
Masoud Kaveh ◽  
Diego Martín ◽  
Mohammad Reza Mosavi
Keyword(s):  
Error Correction ◽  
Random Access ◽  
Error Correction Codes ◽  
Access Memory ◽  
Deep Convolutional Neural Networks ◽  
Device Identification ◽  
Physical Unclonable Functions ◽  
Server Side ◽  
Correction Technique ◽  
Reduction Methods

Traditional authentication techniques, such as cryptographic solutions, are vulnerable to various attacks occurring on session keys and data. Physical unclonable functions (PUFs) such as dynamic random access memory (DRAM)-based PUFs are introduced as promising security blocks to enable cryptography and authentication services. However, PUFs are often sensitive to internal and external noises, which cause reliability issues. The requirement of additional robustness and reliability leads to the involvement of error-reduction methods such as error correction codes (ECCs) and pre-selection schemes that cause considerable extra overheads. In this paper, we propose deep PUF: a deep convolutional neural network (CNN)-based scheme using the latency-based DRAM PUFs without the need for any additional error correction technique. The proposed framework provides a higher number of challenge-response pairs (CRPs) by eliminating the pre-selection and filtering mechanisms. The entire complexity of device identification is moved to the server side that enables the authentication of resource-constrained nodes. The experimental results from a 1Gb DDR3 show that the responses under varying conditions can be classified with at least a 94.9% accuracy rate by using CNN. After applying the proposed authentication steps to the classification results, we show that the probability of identification error can be drastically reduced, which leads to a highly reliable authentication.

Shannon capacities and error-correction codes for optical atmospheric turbulent channels

2005 ◽  
Vol 4 (9) ◽  
pp. 586 ◽  
Author(s):  
Jaime A. Anguita ◽  
Ivan B. Djordjevic ◽  
Mark A. Neifeld ◽  
Bane V. Vasic
Keyword(s):  
Error Correction ◽  
Error Correction Codes

scholarly journals Exponential Golomb and Rice Error Correction Codes for Generalized Near-Capacity Joint Source and Channel Coding

IEEE Access ◽  
2016 ◽  
Vol 4 ◽  
pp. 7154-7175 ◽  
Author(s):  
Matthew F. Brejza ◽  
Tao Wang ◽  
Wenbo Zhang ◽  
David Al-Khalili ◽  
Robert G. Maunder ◽  
...  
Keyword(s):  
Error Correction ◽  
Channel Coding ◽  
Error Correction Codes

A 10T Cell Design without Half Select Problem for Bit-Interleaving Architecture in 65nm CMOS

2013 ◽  
Vol 373-375 ◽  
pp. 1607-1611
Author(s):  
Hong Gang Zhou ◽  
Shou Biao Tan ◽  
Qiang Song ◽  
Chun Yu Peng
Keyword(s):  
Error Correction ◽  
Low Voltage ◽  
Cmos Technology ◽  
Soft Error ◽  
Error Correction Codes ◽  
Cell Design ◽  
Low Voltage Operation ◽  
Sram Cell ◽  
Simulation Results ◽  
Nanometer Regime

With the scaling of process technologies into the nanometer regime, multiple-bit soft error problem becomes more serious. In order to improve the reliability and yield of SRAM, bit-interleaving architecture which integrated with error correction codes (ECC) is commonly used. However, this leads to the half select problem, which involves two aspects: the half select disturb and the additional power caused by half-selected cells. In this paper, we propose a new 10T cell to allow the bit-interleaving array while completely eliminating the half select problem, thus allowing low-power and low-voltage operation. In addition, the RSNM and WM of our proposed 10T cell are improved by 21% and nearly one times, respectively, as compared to the conventional 6T SRAM cell in SMIC 65nm CMOS technology. We also conduct a comparison with the conventional 6T cell about the leakage simulation results, which show 14% of leakage saving in the proposed 10T cell.

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