Design of 8T CNTFET SRAM for Ultra-Low Power Microelectronic Applications

At around 10nm, direct source to drain tunneling in COS-MOS technology constituting fundamental limitations that in turn hold back their suitability for modern electronic appliances chiefly as far as area, energy competency and performance. In advanced electronic appliances, memory constituents play a crucial part. Almost in every digital appliance, memory component is mostly preferred due to its unique potentiality to withhold information. Due to rapid technology advancements, architecture of SRAM is truly tested as far as delay, energy efficiency and stability. Traditional 6T memory unit experiences passage transistor conflict arises the contrast among read balance and write competence. The paper that proposed here contrasts the performance of distinctive CNTFET based 8T memory unit architectures like Traditional and Dual-Port with respect to write delay, read delay and power efficiency like static and dynamic. 8T SRAM bit cell is designed with 32nm CNTFET technology using HSPICE Tool. From the HSPICE simulation results, Dual-Port CNTFET SRAM has provide better read and write delays were reduced by ~8.8% and ~16.3%, static power and dynamic power by ~12.5% and ~42.2% respectively than conventional one.

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Level Converters for Ultra Low Power IoT Applications

International Journal of Engineering & Technology ◽

10.14419/ijet.v7i2.16.11409 ◽

2018 ◽

Vol 7 (2.16) ◽

pp. 19

Author(s):

T Yugendra Chary ◽

S Anitha ◽

M Alamillo ◽

Ameet Chavan

Keyword(s):

Energy Efficiency ◽

Low Power ◽

Slight Reduction ◽

Dramatic Improvement ◽

Modest Improvement ◽

Ultra Low Power ◽

Iot Applications ◽

Communication Devices ◽

And Performance ◽

Level Converter

For efficient ultra-low power IoT applications, working with various communication devices and sensors which operating voltages from subthreshold to superthreshold levels which requires wide variety of robust level converters for signal interfacing with low power dissipation. This paper proposes two topologies of level converter circuits that offer dramatic improvement in power and performance when compared to the existing level converters that shift signals from sub to super threshold levels for IoT applications. At 250 mV, the first proposed circuit - a modification of a tradition al current mirror level converter - offers the best energy efficiency with approximately seven times less energy consumption per operation than the existing design, but suffers from a slight reduction in performance. However, a second proposed circuit - based on a two-stage level converter - at the same voltage enhances performance by several orders of magnitude while still maintaining a modest improvement in energy efficiency. The Energy Delay Products (EDP) of the two proposed designs are equivalent and are approximately four times better than the best existing design. Consequently, the two circuit options either optimizes power or performance with improved overall EDP.

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Exploiting Data-dependencies in Ultra Low-power DSP Arithmetic

VLSI Design ◽

10.1155/2001/94037 ◽

2001 ◽

Vol 12 (3) ◽

pp. 349-363

Author(s):

V. A. Bartlett ◽

E. Grass

Keyword(s):

Energy Efficiency ◽

Energy Consumption ◽

Low Power ◽

Energy Efficient ◽

Dynamic Logic ◽

Low Power Consumption ◽

Ultra Low Power ◽

Data Dependencies ◽

Simulation Results ◽

Asynchronous Environments

Strategies for the design of ultra low power multipliers and multiplier-accumulators are reported. These are optimized for asynchronous applications being able to take advantage of data-dependent computation times. Nevertheless, the low power consumption can be obtained in both synchronous and asynchronous environments. Central to the energy efficiency is a dynamic-logic technique termed Conditional Evaluation which is able to exploit redundancies within the carry-save array and deliver energy consumption which is also heavily data-dependent.Energy efficient adaptations for handling two's complement operands are introduced. Area overheads of the proposed designs are estimated and transistor level simulation results of signed and unsigned multipliers as well as a signed multiplier-accumulator are given.Normalized comparisons with other designs show our approach to use less energy than other published multipliers.

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TI Low-Leakage130nm Digital Process with Nonvolatile FRAM for Ultra-Low-Power Medical Electronics

Journal of Medical Devices ◽

10.1115/1.2932427 ◽

2008 ◽

Vol 2 (2) ◽

Author(s):

A. Robert Landers ◽

B. Jerry Elkind ◽

C. Rajni Aggarwal

Keyword(s):

Low Power ◽

Medical Devices ◽

Active Power ◽

Ultra Low Power ◽

Low Leakage ◽

Low Duty Cycle ◽

Static Power ◽

And Performance ◽

On Chip ◽

Medical Design

Both external and implantable devices are becoming more sophisticated and are requiring more on-chip memory to store data from biological sensors. To deal with this complexity, chip designs are moving toward smaller process geometries, which provide added functionality, reduced size, or both, often along with a reduction in dynamic power. However, leakage power begins to increase significantly at the 130nm node if steps are not taken to mitigate the increased transistor leakage. Lower operating voltages and careful transistor design can offset some of this increase. These very changes, however, make it difficult to design a dense, stable low-power SRAM. Nonvolatile memories like FRAM (F-RAM) avoid these difficulties and save power by simply turning off the memory when not in use. This is particularly valuable since many medical devices have very low duty cycle. FRAM provides the added benefit of providing SRAM-like active power, unlike competing nonvolatile technologies. To meet the challenging power requirements of medical devices, a new ultra-low-power 130nm process has been developed. The new process includes a very-high-density, SER-resistant, nonvolatile FRAM and an ultra-low-leakage transistor, coupled with a library that is optimized for low-power operation. This paper compares the power, area and performance of competing process technologies for a typical implantable medical design and highlights the advantages that FRAM provides in low static power through a transparent power-down capability and in low SRAM-like active power.

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