8-Bit high speed, power efficient SAR ADC designed in 90 nm CMOS technology

2017 ◽  
Author(s):  
Vijay Pratap Singh ◽  
Gaurav Kumar Sharma ◽  
Aasheesh Shukla
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Sar Adc ◽  
Power Efficient

A Linearity Improved 10-bit 120-MS/s 1.5 mW SAR ADC with High-Speed and Low-Noise Dynamic Comparator Technique

2019 ◽  
Vol 29 (06) ◽  
pp. 2050084
Author(s):  
Daiguo Xu ◽  
Hequan Jiang ◽  
Dongbin Fu ◽  
Xiaoquan Yu ◽  
Shiliu Xu ◽  
...  
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Low Noise ◽  
Sar Adc ◽  
Dynamic Comparator ◽  
Analog To Digital ◽  
Input Noise ◽  
Clock Feedthrough ◽  
Threshold Voltages ◽  
Coupled Technique

This paper presents a linearity improved 10-bit 120-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with high-speed and low-noise dynamic comparator. A gate cross-coupled technique is introduced in boost sampling switch, the clock feedthrough effect is compensated without extra auxiliary switch and the linearity of sampling switch is enhanced. Further, substrate voltage boost technique is proposed, the absolute values of threshold voltage and equivalent impedances of MOSFETs are both depressed. Consequently, the delay of comparator is also reduced. Moreover, the reduction of threshold voltages for input MOSFETs could bring higher transconductance and lower equivalent input noise. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 1.5[Formula: see text]mW from 1[Formula: see text]V power supply with a SNDR [Formula: see text][Formula: see text]dB and SFDR [Formula: see text][Formula: see text]dB. The proposed ADC core occupies an active area of 0.021[Formula: see text]mm2, and the corresponding FoM is 24.4 fJ/conversion-step with Nyquist frequency.

scholarly journals A 2.6 GS/s 8-Bit Time-Interleaved SAR ADC in 55 nm CMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 305 ◽  
Author(s):  
Dong Wang ◽  
Xiaoge Zhu ◽  
Xuan Guo ◽  
Jian Luan ◽  
Lei Zhou ◽  
...  
Keyword(s):  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Sar Adc ◽  
Oxide Semiconductor ◽  
Power Measurement ◽  
Cmos Process ◽  
Analog To Digital ◽  
Full Speed ◽  
Time Interleaved

This paper presents an eight-channel time-interleaved (TI) 2.6 GS/s 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) prototype in a 55-nm complementary metal-oxide-semiconductor (CMOS) process. The channel-selection-embedded bootstrap switch is adopted to perform sampling times synchronization using the full-speed master clock to suppress the time skew between channels. Based on the segmented pre-quantization and bypass switching scheme, double alternate comparators clocked asynchronously with background offset calibration are utilized in sub-channel SAR ADC to achieve high speed and low power. Measurement results show that the signal-to-noise-and-distortion ratio (SNDR) of the ADC is above 38.2 dB up to 500 MHz input frequency and above 31.8 dB across the entire first Nyquist zone. The differential non-linearity (DNL) and integral non-linearity (INL) are +0.93/−0.85 LSB and +0.71/−0.91 LSB, respectively. The ADC consumes 60 mW from a 1.2 V supply, occupies an area of 400 μm × 550 μm, and exhibits a figure-of-merit (FoM) of 348 fJ/conversion-step.

A Low-Power, Signal-Specific SAR ADC for Neural Sensing Applications

2018 ◽  
Vol 27 (14) ◽  
pp. 1850230 ◽  
Author(s):  
Samaneh Babayan-Mashhadi ◽  
Mona Jahangiri-Khah
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Sampling Rate ◽  
Power Saving ◽  
Cmos Technology ◽  
Sar Adc ◽  
Signal Acquisition ◽  
Quantization Scheme ◽  
Power Efficient ◽  
Sensing Applications

As power consumption is one of the major issues in biomedical implantable devices, in this paper, a novel quantization method is proposed for successive approximation register (SAR) analog-to-digital converters (ADCs) which can save 80% power consumption in contrast to conventional structure for electroencephalogram (EEG) signal recording systems. According to the characteristics of neural signals, the principle of the proposed power saving technique was inspired such that only the difference between current input sample and the previous one is quantized, using a power efficient SAR ADC with fewer resolutions. To verify the proposed quantization scheme, the ADC is systematically modeled in Matlab and designed and simulated in circuit level using 0.18[Formula: see text][Formula: see text]m CMOS technology. When applied to neural signal acquisition, spice simulations show that at sampling rate of 25[Formula: see text]kS/s, the proposed 8-bit ADC consumes 260[Formula: see text]nW of power from 1.8[Formula: see text]V supply voltage while achieving 7.1 effective number of bits.

scholarly journals Design of Area and Power Efficient Multiplier Unit using Wallace Tree Algorithm

2020 ◽  
Vol 9 (1) ◽  
pp. 1350-1354
Keyword(s):  
High Speed ◽  
Processing System ◽  
Cmos Technology ◽  
Time Signal ◽  
Processing Unit ◽  
Productive Capacity ◽  
Tree Algorithm ◽  
Power Efficient ◽  
Wallace Tree ◽  
Unit Performance

In any processing system, the core data path element may be a multiplier that particularly associated with DSP applications, which concludes overall processing unit performance. In such system, the multiplier unit improves the performance will boost up the potential. The Cadence EDA performs for high-speed multiplier evaluation consisting 64 x 64 bit in ASIC Digital flow (RTL-GDSII). Using carry select adder and carry save adder, the proposed multiplier intend with Wallace structure for enhancing the speed criteria. Wallace rebate absorbs more time for designing because it is more complex and aberrant in format for better width. Real Time signal processor requires high productive capacity and fewer reaction time. A classic scheme could be today in IOT utilizations. The proposed method concentrates on designing low power and area efficient in digital flow using the Wallace tree algorithm. The 180 nm CMOS technology for pursuance and outcome are related with other existing methods in delay, area and dynamic power dissipation.

scholarly journals High Speed Power Efficient CMOS Inverter Based Current Comparator in UMC 90 nm Technology

2016 ◽  
Vol 6 (1) ◽  
pp. 90
Author(s):  
Veepsa Bhatia ◽  
Neeta Pandey ◽  
Asok Bhattacharyya
Keyword(s):  
High Speed ◽  
Supply Voltage ◽  
Average Power ◽  
Current Mode ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Cmos Inverter ◽  
Power Efficient ◽  
Current Comparator ◽  
Average Power Consumption

A novel power-speed efficient current comparator is proposed in this paper. It comprises of only CMOS inverters in its structure, employing a simple biasing method. The structure offers simplicity of design. It posesses the very desirable features of high speed and low power dissipation, making this structure a highly desirable one for various current mode applications. The simulations have been performed using UMC 90 nm CMOS technology and the results demonstrate the propagation delay of about 3.1 ns and the average power consumption of 24.3 µW for 300 nA input current at supply voltage of 1V.

scholarly journals A Digital-to-Time Converter for Time-Mode Successive-Approximation Register Analog-to-Digital Converters

2021 ◽  
Author(s):  
Daniel Junehee Lee
Keyword(s):  
Power Consumption ◽  
Successive Approximation ◽  
Cmos Technology ◽  
Sar Adc ◽  
Least Significant Bit ◽  
Silicon Area ◽  
Analog To Digital ◽  
Power Efficient ◽  
Successive Approximation Register ◽  
Simulation Results

file:///C:/Users/MWF/Downloads/Lee, Daniel Junehee.The 8-bit digital-to-time converter (DTC) to be used for a time-mode successive-approximation register analog-to-digital converter (SAR ADC) with a minimum power consumption and silicon area is presented. The architecture and the drawbacks of a conventional voltage-mode SAR ADC are discussed. The principle of time-mode circuits and benefits of their applications to mixed-signal circuits are explained. The architecture of a time-mode SAR ADC is presented. The need for an area and power-efficient DTC to be used for a time-mode SAR ADC is discussed. The principle of a DTC is explained and prior works on a DTC are reviewed. The principle of a phase interpolator (PI), to be used for a DTC, is explained and prior works on digital PIs are reviewed. The design of the proposed DTC is presented. Each block of the proposed DTC is explained using schematic and layout views. Optimal slope of the input of the PI and the condition for linear phase interpolation are investigated. Simulation results of the proposed DTC designed in TSMC 65 nm 1.0 V CMOS technology are provided. According to simulation results with BSIM4.4 device models only, the time resolution of 0.33 ps, a maximum operation frequency of 2.53 G Hz, the power consumption of 1.38 mW, and peak differential nonlinearity (DNL) and integral nonlinearity (INL) less than 0.14 least significant bit (LSB) and 0.49 LSB, respectively, for a nominal process (TT) and a temperature condition (27 C°) are achieved.

scholarly journals A 14-bit 10kS/s power efficient 65nm SAR ADC for cardiac implantable medical devices

2018 ◽  
Vol 7 (2.8) ◽  
pp. 30 ◽  
Author(s):  
Bala Dastagiri Nadhindla ◽  
K Hari Kishore
Keyword(s):  
Supply Voltage ◽  
Cmos Technology ◽  
Sar Adc ◽  
Implantable Medical Devices ◽  
Efficient Operation ◽  
Analog To Digital ◽  
Power Efficient ◽  
Capacitive Dac ◽  
Latched Comparator ◽  
Binary Weighted

This brief presents a 10kS/s 14 bit 12.5 ENOB Successive Approximation Register Analog-to- Digital Converter for Cardiac Implantable Medical. For achieving power efficient operation, SAR ADC employ SAR control, a new power and noise efficient comparator topology, non- binary weighted capacitive DAC. The linearity of implemented SAR ADC is enhanced with the uniform geometry of non-binary weighted capacitive DAC.The proposed SAR ADC is implemented using 65nm CMOS technology. The latched comparator consumes a power of 2.4uW and it provides an ENOB of 12.6 at a supply voltage of 1V.The INL is between -2.7/+1.6 LSB and DNL is between -0.6/+1.4LSB. The FOM of ADC is 40fJ/conv. Step which is comparable with existing ADC topologies.

High Speed Power Efficient CMOS Inverter Based Current Comparator in UMC 90 nm Technology

2016 ◽  
Vol 6 (1) ◽  
pp. 90 ◽  
Author(s):  
Veepsa Bhatia ◽  
Neeta Pandey ◽  
Asok Bhattacharyya
Keyword(s):  
High Speed ◽  
Supply Voltage ◽  
Average Power ◽  
Current Mode ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Cmos Inverter ◽  
Power Efficient ◽  
Current Comparator ◽  
Average Power Consumption

A novel power-speed efficient current comparator is proposed in this paper. It comprises of only CMOS inverters in its structure, employing a simple biasing method. The structure offers simplicity of design. It posesses the very desirable features of high speed and low power dissipation, making this structure a highly desirable one for various current mode applications. The simulations have been performed using UMC 90 nm CMOS technology and the results demonstrate the propagation delay of about 3.1 ns and the average power consumption of 24.3 µW for 300 nA input current at supply voltage of 1V.

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