A high performance 3-bit ripple counter circuit based on Organic TFTs for flexible read out integrated circuit

2019 ◽  
pp. 1634
Author(s):  
Hansai Ji ◽  
Di Geng ◽  
Yuxin Gong ◽  
Qian Chen ◽  
Xinlv Duan ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Counter Circuit

PERFORMANCE AT THE EDGE: GALLIUM ARSENIDE AND SILICON ICs FOR OPTICAL ELECTRONICS

1991 ◽  
Vol 02 (03) ◽  
pp. 147-162 ◽  
Author(s):  
ROBERT G. SWARTZ
Keyword(s):  
Gallium Arsenide ◽  
Optical Communication ◽  
Optical Communications ◽  
Integrated Circuit ◽  
High Performance ◽  
Compound Semiconductor ◽  
Performance Curve ◽  
Semiconductor Technology ◽  
Market Trends ◽  
Circuit Technology

Compound semiconductor technology is rapidly entering the mainstream, and is quickly finding its way into consumer applications where high performance is paramount. But silicon integrated circuit technology is evolving up the performance curve, and CMOS in particular is consuming ever more market share. Nowhere is this contest more clearly evident than in optical communications. Here applications demand performance ranging from a few hundreds of megahertz to multi-gigahertz, from circuits containing anywhere from tens to tens of thousands of devices. This paper reviews the high performance electronics found in optical communication applications from a technology standpoint, illustrating merits and market trends for these competing, yet often complementary IC technologies.

3D Stacks of Microprocessors and Memories With Backside Two-Phase Multi-Microchannel Cooler

2013 ◽  
Author(s):  
Jackson B. Marcinichen ◽  
John R. Thome
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Flow Distribution ◽  
Two Phase ◽  
Hydrodynamic Simulations ◽  
3D Ics ◽  
Technological Advances ◽  
High Level ◽  
Transfer Of Information ◽  
High Performance Computers

For the next generation of high performance computers, the new challenges are to shorten the distance for transporting data (to accelerate the transfer of information) between multi-microprocessors and memories, and to cool these electronic components despite the increased heat flux that results from increased transistor density. Recent technological advances show a tendency for the development of 3D integrated circuit stacked architectures with interlayer cooling (multi-microchannels in the silicon layers). However, huge challenges exist in such design/concept, i.e. flow distribution to hundreds microchannels distributed in the different interlayers, thermo-hydrodynamic and geometrical limitations, manufacturing etc. 3D-ICs with interlayer cooling are still about a decade away, so a viable shorter term goal is 3D stacks with backside cooling, taking advantage of Si layers now able to be thineer down to only 50 μm thickness. Thus, the present work presents thermo-hydrodynamic simulations for 3D stacks considering only a backside cooler, which simplifies considerably the assembly and guarantees a high level of reliability. In summary, the results showed that this concept is thermally feasible and potentially that interlayer microchannels (between stacks) will not be necessary.

Reliability evaluation of wearable radio frequency identification tags: Design and fabrication of a two-part textile antenna

2018 ◽  
Vol 89 (4) ◽  
pp. 560-571 ◽  
Author(s):  
Xiaochen Chen ◽  
Leena Ukkonen ◽  
Johanna Virkki
Keyword(s):  
Radio Frequency ◽  
Radio Frequency Identification ◽  
Integrated Circuit ◽  
High Performance ◽  
Cyclic Strain ◽  
Moist Environment ◽  
Frequency Identification ◽  
Identification Tags ◽  
Cost Efficient ◽  
The One

Passive radio frequency identification-based technology is a convincing approach to the achievement of versatile energy- and cost-efficient wireless platforms for future wearable applications. By using two-part antenna structures, the antenna-electronics interconnections can remain non-stressed, which can significantly improve the reliability of the textile-embedded wireless components. In this article, we describe fabrication of two-part stretchable and non-stretchable passive ultra-high frequency radio frequency identification textile tags using electro-textile and embroidered antennas, and test their reliability when immersed as well as under cyclic strain. The results are compared to tags with traditional one-part dipole antennas fabricated from electro-textiles and by embroidery. Based on the results achieved, the initial read ranges of the two-part antenna tags, around 5 m, were only slightly shorter than those of the one-part antenna tags. In addition, the tag with two-part antennas can maintain high performance in a moist environment and during continuous stretching, unlike the one-part antenna tag where the antenna-integrated circuit attachment is under stress.

High-Performance Reconfigurable Computing

2019 ◽  
pp. 731-744
Author(s):  
Mário Pereira Vestias
Keyword(s):  
Power Consumption ◽  
Integrated Circuit ◽  
Reconfigurable Computing ◽  
High Performance ◽  
General Purpose ◽  
Reconfigurable Hardware ◽  
Coarse Grained ◽  
Lower Power ◽  
Fine Grained ◽  
Application Specific

High-performance reconfigurable computing systems integrate reconfigurable technology in the computing architecture to improve performance. Besides performance, reconfigurable hardware devices also achieve lower power consumption compared to general-purpose processors. Better performance and lower power consumption could be achieved using application-specific integrated circuit (ASIC) technology. However, ASICs are not reconfigurable, turning them application specific. Reconfigurable logic becomes a major advantage when hardware flexibility permits to speed up whatever the application with the same hardware module. The first and most common devices utilized for reconfigurable computing are fine-grained FPGAs with a large hardware flexibility. To reduce the performance and area overhead associated with the reconfigurability, coarse-grained reconfigurable solutions has been proposed as a way to achieve better performance and lower power consumption. In this chapter, the authors provide a description of reconfigurable hardware for high-performance computing.

High-Performance Reconfigurable Computing

2018 ◽  
pp. 4018-4029
Author(s):  
Mário Pereira Vestias
Keyword(s):  
Power Consumption ◽  
Integrated Circuit ◽  
Reconfigurable Computing ◽  
High Performance ◽  
General Purpose ◽  
Reconfigurable Hardware ◽  
Coarse Grained ◽  
Lower Power ◽  
Fine Grained ◽  
Application Specific

High-Performance Reconfigurable Computing systems integrate reconfigurable technology in the computing architecture to improve performance. Besides performance, reconfigurable hardware devices also achieve lower power consumption compared to General-Purpose Processors. Better performance and lower power consumption could be achieved using Application Specific Integrated Circuit (ASIC) technology. However, ASICs are not reconfigurable, turning them application specific. Reconfigurable logic becomes a major advantage when hardware flexibility permits to speed up whatever the application with the same hardware module. The first and most common devices utilized for reconfigurable computing are fine-grained FPGAs with a large hardware flexibility. To reduce the performance and area overhead associated with the reconfigurability, coarse-grained reconfigurable solutions has been proposed as a way to achieve better performance and lower power consumption. In this chapter we will provide a description of reconfigurable hardware for high performance computing.

Package Voltage Regulators: The Answer for Power Management Challenges

2019 ◽  
Vol 2019 (1) ◽  
pp. 000438-000443 ◽  
Author(s):  
Joseph Meyer ◽  
Reza Moghimi ◽  
Noah Sturcken
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Power Conversion ◽  
Cmos Technology ◽  
Voltage Regulation ◽  
Voltage Regulators ◽  
Electronic Systems ◽  
Single Chip ◽  
Fully Integrated ◽  
Computational Performance

Abstract The generational scaling of CMOS device geometries, as predicted by Moore's law, has significantly outpaced advances in CMOS package and power electronics technology. The conduction of power to a high-performance integrated circuit (IC) die typically requires close to 50% of package and IC I/O and is increasing with trends towards lower supply voltages and higher power density that occur in advanced CMOS nodes. The disparity in scaling of logic, package, and I/O technology has created a significant bottleneck that has become a dominant constraint on computational performance. By performing power conversion and voltage regulation in-package, this limitation can be mitigated. Integration of thin-film ferromagnetic inductors with CMOS technology enables single-chip power converters to be co-packaged with processors, high bandwidth memory (HBM), and/or other modules. This paper highlights the advantages of fully integrated package voltage regulators (PVRs), which include: reducing package I/O allocated for power, eliminating the need for upstream power-conversion stages, and improving transient response. These benefits substantially reduce the size, weight, and power of modern electronic systems.

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