Package Voltage Regulators: The Answer for Power Management Challenges

2019 ◽  
Vol 2019 (1) ◽  
pp. 000438-000443 ◽  
Author(s):  
Joseph Meyer ◽  
Reza Moghimi ◽  
Noah Sturcken
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Power Conversion ◽  
Cmos Technology ◽  
Voltage Regulation ◽  
Voltage Regulators ◽  
Electronic Systems ◽  
Single Chip ◽  
Fully Integrated ◽  
Computational Performance

Abstract The generational scaling of CMOS device geometries, as predicted by Moore's law, has significantly outpaced advances in CMOS package and power electronics technology. The conduction of power to a high-performance integrated circuit (IC) die typically requires close to 50% of package and IC I/O and is increasing with trends towards lower supply voltages and higher power density that occur in advanced CMOS nodes. The disparity in scaling of logic, package, and I/O technology has created a significant bottleneck that has become a dominant constraint on computational performance. By performing power conversion and voltage regulation in-package, this limitation can be mitigated. Integration of thin-film ferromagnetic inductors with CMOS technology enables single-chip power converters to be co-packaged with processors, high bandwidth memory (HBM), and/or other modules. This paper highlights the advantages of fully integrated package voltage regulators (PVRs), which include: reducing package I/O allocated for power, eliminating the need for upstream power-conversion stages, and improving transient response. These benefits substantially reduce the size, weight, and power of modern electronic systems.

A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA

2013 ◽  
Vol 22 (10) ◽  
pp. 1340033 ◽  
Author(s):  
HONGLIANG ZHAO ◽  
YIQIANG ZHAO ◽  
YIWEI SONG ◽  
JUN LIAO ◽  
JUNFENG GENG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Readout Integrated Circuit ◽  
Chip Area ◽  
Operating Modes

A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm2. By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm2.

Integrated Optoelectronic Devices on Silicon

2012 ◽  
Vol 1396 ◽  
Author(s):  
Di Liang ◽  
John E. Bowers
Keyword(s):  
Output Power ◽  
Integrated Circuit ◽  
High Speed ◽  
High Performance ◽  
Continuous Wave ◽  
Light Emission ◽  
Extinction Ratio ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Pockels Effect

ABSTRACTSilicon (Si) has been the dominating material platform of microelectronics over half century. Continuous technological advances in circuit design and manufacturing enable complementary metal-oxide semiconductor (CMOS) chips with increasingly high integration complexity to be fabricated in an unprecedently scale and economical manner. Conventional Si-based planar lightwave circuits (PLCs) has benefited from advanced CMOS technology but only demonstrate passive functionalities in most circumstances due to poor light emission efficiency and weak major electro-optic effects (e.g., Pockels effect, the Kerr effect and the Franz–Keldysh effect) in Si. Recently, a new hybrid III-V-on-Si integration platform has been developed, aiming to bridge the gap between Si and III-V direct-bandgap materials for active Si photonic integrated circuit applications. Since then high-performance lasers, amplifiers, photodetectors and modulators, etc. have been demonstrated. Here we review the most recent progress on hybrid Si lasers and high-speed hybrid Si modulators. The former include distributed feedback (DFB) lasers showing over 10 mW output power and up to 85 oC continuous-wave (cw) operation, compact hybrid microring lasers with cw threshold less than 4 mA and over 3 mW output power, and 4-channel hybrid Si AWG lasers with channel space of 360 GHz. Recently fabricated traveling-wave electro-absorption modulators (EAMs) and Mach-Zehnder interferometer modulators (MZM) on this platform support 50 Gb/s and 40 Gb/s data transmission with over 10 dB extinction ratio, respectively.

Low Power High Performance Full Adder Design Using Gate Diffusion Input Techniques

2020 ◽  
Vol 17 (4) ◽  
pp. 1595-1599
Author(s):  
N. Suresh ◽  
K. Subba Rao ◽  
R. Vassoudevan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Large Scale ◽  
Digital Signal ◽  
Full Adder ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Essential Components

Very Large Scale Integrated (VLSI) technology for a widespread use of high performance portable integrated circuit (IC) devices such as MP3, PDA, mobile phones is increasing rapidly. Most of the VLSI applications, such as digital signal processing, image processing and microprocessors, extensively use arithmetic operations. In this research novel low power full adder architecture has been proposed for various applications which uses the advanced adder and multiplier designs. A full-adder is one of the essential components in digital circuit design; many improvements have been made to reduce the architecture of a full adder. In this research modified full adder using GDI technique is proposed to achieve low power consumption. By using GDI cell, the transistor count is greatly reduced, thereby reducing the power consumption and propagation delay while maintaining the low complexity of the logic design. The parameters in terms of Power, Delay, and Surface area are investigated by comparison of the proposed GDI technology with an optimized 90 nm CMOS technology.

scholarly journals Low-power ASIC suitable for miniaturized wireless EMG systems

2019 ◽  
Vol 70 (5) ◽  
pp. 393-399 ◽  
Author(s):  
Vilem Kledrowetz ◽  
Roman Prokop ◽  
Lukas Fujcik ◽  
Michal Pavlik ◽  
Jiří Háze
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Low Voltage ◽  
Cmos Technology ◽  
Instrumentation Amplifier ◽  
Pass Filter ◽  
Delta Sigma ◽  
Pulse Density ◽  
Wide Range

Abstract Nowadays, the technology advancements of signal processing, low-voltage low-power circuits and miniaturized circuits have enabled the design of compact, battery-powered, high performance solutions for a wide range of, particularly, biomedical applications. Novel sensors for human biomedical signals are creating new opportunities for low weight wearable devices which allow continuous monitoring together with freedom of movement of the users. This paper presents the design and implementation of a novel miniaturized low-power sensor in integrated circuit (IC) form suitable for wireless electromyogram (EMG) systems. Signal inputs (electrodes) are connected to this application-specific integrated circuit (ASIC). The ASIC consists of several consecutive parts. Signals from electrodes are fed to an instrumentation amplifier (INA) with fixed gain of 50 and filtered by two filters (a low-pass and high-pass filter), which remove useless signals and noise with frequencies below 20 Hz and above 500 Hz. Then signal is amplified by a variable gain amplifier. The INA together with the reconfigurable amplifier provide overall gain of 50, 200, 500 or 1250. The amplified signal is then converted to pulse density modulated (PDM) signal using a 12-bit delta-sigma modulator. The ASIC is fabricated in TSMC0.18 mixed-signal CMOS technology.

A Reliable, Low Power and Nonvolatile MTJ-Based Flip-Flop for Advanced Nanoelectronics

2018 ◽  
Vol 27 (13) ◽  
pp. 1850205 ◽  
Author(s):  
Ramin Rajaei
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Radiation Effects ◽  
Large Scale ◽  
Vlsi Design ◽  
Magnetic Tunnel Junction ◽  
Cmos Technology ◽  
Flip Flop ◽  
Reliability Challenge

Very large-scale integrated circuit (VLSI) design faces many challenges with today’s nanometer CMOS technology, including leakage current and reliability issues. Magnetic tunnel junction (MTJ) hybrid with CMOS transistors can offer many advantages for future VLSI design such as high performance, low power consumption, easy integration with CMOS and also nonvolatility. However, MTJ-based logic circuits suffer from a reliability challenge that is the read disturbance issue. This paper proposes a new nonvolatile magnetic flip-flop (MFF) that offers a disturbance-free sensing and a low power write operation over the previous MFFs. This magnetic-based logic circuit is based on the previous two-in-one (TIO) MTJ cell that presents the aforementioned attributes. Radiation-induced single event upset, as another reliability challenge, is also taken into consideration for the MFFs and another MFF robust against radiation effects is suggested and evaluated.

LEAKAGE POWER REDUCTION OF ASYNCHRONOUS PIPELINES

2011 ◽  
Vol 20 (02) ◽  
pp. 207-222
Author(s):  
BEHNAM GHAVAMI ◽  
HOSSEIN PEDRAM ◽  
AREZOO SALARPOUR
Keyword(s):  
Threshold Voltage ◽  
High Performance ◽  
Graph Model ◽  
Cmos Technology ◽  
Leakage Power ◽  
Total Power ◽  
High Threshold ◽  
Single Chip ◽  
Technology Scaling ◽  
Performance Penalty

With CMOS technology scaling, leakage power is expected to become a significant portion of the total power. A dual-threshold CMOS circuit, which has both high and low threshold transistors in a single chip, can be used to deal with the leakage problem in high performance applications. This paper presents dual-threshold voltage technique for reducing leakage power dissipation of Quasi Delay Insensitive asynchronous pipelines while still maintaining high performance of these circuits. We exploited the Dependency Graph model to produce a formal performance analysis. In order to reduce leakage power an efficient algorithm for selecting and assigning high threshold voltage to templates of a pipeline is proposed. Results obtained indicate that our proposed technique can achieve on average 40% savings for leakage power, while there is no performance penalty.

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