PERFORMANCE AT THE EDGE: GALLIUM ARSENIDE AND SILICON ICs FOR OPTICAL ELECTRONICS

1991 ◽  
Vol 02 (03) ◽  
pp. 147-162 ◽  
Author(s):  
ROBERT G. SWARTZ
Keyword(s):  
Gallium Arsenide ◽  
Optical Communication ◽  
Optical Communications ◽  
Integrated Circuit ◽  
High Performance ◽  
Compound Semiconductor ◽  
Performance Curve ◽  
Semiconductor Technology ◽  
Market Trends ◽  
Circuit Technology

Compound semiconductor technology is rapidly entering the mainstream, and is quickly finding its way into consumer applications where high performance is paramount. But silicon integrated circuit technology is evolving up the performance curve, and CMOS in particular is consuming ever more market share. Nowhere is this contest more clearly evident than in optical communications. Here applications demand performance ranging from a few hundreds of megahertz to multi-gigahertz, from circuits containing anywhere from tens to tens of thousands of devices. This paper reviews the high performance electronics found in optical communication applications from a technology standpoint, illustrating merits and market trends for these competing, yet often complementary IC technologies.

scholarly journals Giga-Scale Integration System-On-A-Chip Design: Challenges and Noteworthy Solutions

2020 ◽  
Vol 8 (6) ◽  
pp. 741-746
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Chip Design ◽  
Future Challenges ◽  
System On A Chip ◽  
And Performance ◽  
Exponential Rates ◽  
Scale Integration ◽  
Bus Architecture ◽  
Circuit Technology

In all respects of the last five decades, integrated circuit technology has advanced at exponential rates in both productivity and performance. Giga-Scale Integration (GSI) System-On-A-Chip (SoC) designs have become one of the main drivers of the integrated circuit technology in recent years. The objective of this work is to understand the challenges of Giga-scale SoC integration in nanometer technologies, and identify promising conveniences for innovation. Physical designs are crucial for SoC integration and in our work we identify them with details. In future the couplings and interactions among system components will increase as we put more of the system on a silicon die. Therefore the system designers will face challenges in several areas and we describe these future challenges briefly. Developing a design driver for GSI SoC design is important. With the help of this design driver we provide the design methodology, which ensures the high performance of the design. We present two noteworthy solutions which overcome the challenges of GSI SoC design. One is reuse and integration and another is efficient bus architecture. We also provide the challenges for verification of GSI SoC and methods to overcome these challenges.

Preparation of TEM samples by focused ion beams

1995 ◽  
Vol 53 ◽  
pp. 518-519
Author(s):  
John F. Walker ◽  
J C Reiner ◽  
C Solenthaler
Keyword(s):  
Integrated Circuit ◽  
Polycrystalline Silicon ◽  
Field Effect Transistor ◽  
High Spatial Resolution ◽  
Ion Beam ◽  
Ion Beams ◽  
Focused Ion Beams ◽  
Precise Location ◽  
Effect Transistor ◽  
Circuit Technology

The high spatial resolution available from TEM can be used with great advantage in the field of microelectronics to identify problems associated with the continually shrinking geometries of integrated circuit technology. In many cases the location of the problem can be the most problematic element of sample preparation. Focused ion beams (FIB) have previously been used to prepare TEM specimens, but not including using the ion beam imaging capabilities to locate a buried feature of interest. Here we describe how a defect has been located using the ability of a FIB to both mill a section and to search for a defect whose precise location is unknown. The defect is known from electrical leakage measurements to be a break in the gate oxide of a field effect transistor. The gate is a square of polycrystalline silicon, approximately 1μm×1μm, on a silicon dioxide barrier which is about 17nm thick. The break in the oxide can occur anywhere within that square and is expected to be less than 100nm in diameter.

Gallium Arsenide Photonic Integrated Circuit Platform for Tunable Laser Applications

2021 ◽  
pp. 1-1
Author(s):  
Paul Verrinder ◽  
Lei Wang ◽  
Joseph Fridlander ◽  
Fengqiao Sang ◽  
Victoria Rosborough ◽  
...  
Keyword(s):  
Gallium Arsenide ◽  
Integrated Circuit ◽  
Tunable Laser ◽  
Laser Applications ◽  
Photonic Integrated Circuit

scholarly journals Design and Development of a 3dB Quadrature Patch Hybrid Coupler

2018 ◽  
Vol 7 (2.6) ◽  
pp. 217
Author(s):  
B Sekharbabu ◽  
K Narsimha Reddy ◽  
S Sreenu
Keyword(s):  
Integrated Circuit ◽  
High Frequency ◽  
Return Loss ◽  
Coupling Factor ◽  
Power Combiners ◽  
Measurement Results ◽  
Structure Simulation ◽  
Hybrid Coupler ◽  
Port Device ◽  
Circuit Technology

In this paper a -3 dB, 90-degreephase shift RF quadrature patch hybrid coupler is designed to operate at 2.4GHz. Hybrid coupler is a four-port device, that’s accustomed split a signaling with a resultant 90degrees’ section shift between output signals whereas maintaining high isolation between the output ports. The RF quadrature patch hybrid coupler is used in various radio frequency applications including mixers, power combiners, dividers, modulators and amplifiers. The desired hybrid coupler is designed using FR-4 substrate with 1.6mm height in High Frequency Structure Simulation (HFSS) and the same is fabricated and tested. The designed Hybrid coupler is examined in terms of parameters like insertion Loss, coupling factor and return Loss. The simulation and measurement results are compared. Major advantages of the RF quadrature patch hybrid couplers are that they are compatible with integrated circuit technology.

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