scholarly journals SVM-based switching filter hardware design for mixed noise reduction in digital images using high-level synthesis tools

2022 ◽  
Vol 12 (1) ◽  
pp. 0-0
Keyword(s):  
Image Quality ◽  
Support Vector Machine Classifier ◽  
Digital Images ◽  
High Level Synthesis ◽  
Support Vector ◽  
Hardware Accelerator ◽  
Mixed Noise ◽  
High Level ◽  
Switching Filter ◽  
Better Than

Impulse and Gaussian are the two most common types of noise that affect digital images due to imperfections in the imaging process, compression, storage and communication. The conventional filtering approaches, however, reduce the image quality in terms of sharpness and resolution while suppressing the effects of noise. In this work, a machine learning-based filtering structure has been proposed preserves the image quality while effectively removing the noise. Specifically, a support vector machine classifier is employed to detect the type of noise affecting each pixel to select an appropriate filter. The choice of filters includes Median and Bilateral filters of different kernel sizes. The classifier is trained using example images with known noise parameters. The proposed filtering structure has been shown to perform better than the conventional approaches in terms of image quality metrics. Moreover, the design has been implemented as a hardware accelerator on an FPGA device using high-level synthesis tools.

scholarly journals High-Level Synthesis of Multiclass SVM Using Code Refactoring to Classify Brain Cancer from Hyperspectral Images

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1494 ◽  
Author(s):  
Abelardo Baez ◽  
Himar Fabelo ◽  
Samuel Ortega ◽  
Giordana Florimbi ◽  
Emanuele Torti ◽  
...  
Keyword(s):  
Brain Cancer ◽  
Research Field ◽  
Hyperspectral Images ◽  
High Level Synthesis ◽  
Support Vector ◽  
Svm Classifier ◽  
Code Refactoring ◽  
Field Programmable ◽  
And Performance ◽  
High Level

Currently, high-level synthesis (HLS) methods and tools are a highly relevant area in the strategy of several leading companies in the field of system-on-chips (SoCs) and field programmable gate arrays (FPGAs). HLS facilitates the work of system developers, who benefit from integrated and automated design workflows, considerably reducing the design time. Although many advances have been made in this research field, there are still some uncertainties about the quality and performance of the designs generated with the use of HLS methodologies. In this paper, we propose an optimization of the HLS methodology by code refactoring using Xilinx SDSoCTM (Software-Defined System-On-Chip). Several options were analyzed for each alternative through code refactoring of a multiclass support vector machine (SVM) classifier written in C, using two different Zynq®-7000 SoC devices from Xilinx, the ZC7020 (ZedBoard) and the ZC7045 (ZC706). The classifier was evaluated using a brain cancer database of hyperspectral images. The proposed methodology not only reduces the required resources using less than 20% of the FPGA, but also reduces the power consumption −23% compared to the full implementation. The speedup obtained of 2.86× (ZC7045) is the highest found in the literature for SVM hardware implementations.

scholarly journals A High-Level Synthesis Implementation and Evaluation of an Image Processing Accelerator

Technologies ◽  
2018 ◽  
Vol 7 (1) ◽  
pp. 4
Author(s):  
Dimitris Tsiktsiris ◽  
Dimitris Ziouzios ◽  
Minas Dasygenis
Keyword(s):  
Image Processing ◽  
Edge Detection ◽  
Digital Image Processing ◽  
Digital Image ◽  
High Level Synthesis ◽  
Bare Metal ◽  
Sobel Edge Detection ◽  
High Level ◽  
Graphics Processing ◽  
Better Than

Most frequently, an FPGA is used as an implementation platform in applications of graphics processing, as its structure can effectively exploit both spatial and temporal parallelism. Such parallelization techniques involve fundamental restrictions, namely being their dependence on both the processing model and the system’s hardware constraints, that can force the designer to restructure the architecture and the implementation. Predesigned accelerators can significantly assist the designer to solve this problem and meet his deadlines. In this paper, we present our accelerators for Grayscale and Sobel Edge Detection, two of the most fundamental algorithms used in digital image processing projects. We have implemented those algorithms with a “bare-metal” VHDL design, written purely by hand, as a portable USB accelerator device, as well as an HLS-based overlay of a similar implementation designed to be used by a Python interface. The comparisons of the two architectures showcase that the HLS generated design can perform equally to or even better than the handwritten HDL equivalent, especially when the correct compiler directives are provided.

scholarly journals High-Level Synthesis of Online K-Means Clustering Hardware for a Real-Time Image Processing Pipeline

2019 ◽  
Vol 5 (3) ◽  
pp. 38 ◽  
Author(s):  
Aiman Badawi ◽  
Muhammad Bilal
Keyword(s):  
Image Processing ◽  
Image Segmentation ◽  
Real Time ◽  
Moving Average ◽  
Weighted Average ◽  
High Level Synthesis ◽  
Hardware Accelerator ◽  
Hardware Complexity ◽  
Processing Pipeline ◽  
High Level

The growing need for smart surveillance solutions requires that modern video capturing devices to be equipped with advance features, such as object detection, scene characterization, and event detection, etc. Image segmentation into various connected regions is a vital pre-processing step in these and other advanced computer vision algorithms. Thus, the inclusion of a hardware accelerator for this task in the conventional image processing pipeline inevitably reduces the workload for more advanced operations downstream. Moreover, design entry by using high-level synthesis tools is gaining popularity for the facilitation of system development under a rapid prototyping paradigm. To address these design requirements, we have developed a hardware accelerator for image segmentation, based on an online K-Means algorithm using a Simulink high-level synthesis tool. The developed hardware uses a standard pixel streaming protocol, and it can be readily inserted into any image processing pipeline as an Intellectual Property (IP) core on a Field Programmable Gate Array (FPGA). Furthermore, the proposed design reduces the hardware complexity of the conventional architectures by employing a weighted instead of a moving average to update the clusters. Experimental evidence has also been provided to demonstrate that the proposed weighted average-based approach yields better results than the conventional moving average on test video sequences. The synthesized hardware has been tested in real-time environment to process Full HD video at 26.5 fps, while the estimated dynamic power consumption is less than 90 mW on the Xilinx Zynq-7000 SOC.

scholarly journals Algorithmic-Level Approximate Tensorial SVM Using High-Level Synthesis on FPGA

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 205
Author(s):  
Hamoud Younes ◽  
Ali Ibrahim ◽  
Mostafa Rizk ◽  
Maurizio Valle
Keyword(s):  
Machine Learning ◽  
State Of The Art ◽  
Machine Learning Algorithms ◽  
High Level Synthesis ◽  
Support Vector ◽  
Svm Classifier ◽  
Approximate Computing ◽  
Classification Framework ◽  
Time Latency ◽  
High Level

Approximate Computing Techniques (ACT) are promising solutions towards the achievement of reduced energy, time latency and hardware size for embedded implementations of machine learning algorithms. In this paper, we present the first FPGA implementation of an approximate tensorial Support Vector Machine (SVM) classifier with algorithmic level ACTs using High-Level Synthesis (HLS). A touch modality classification framework was adopted to validate the effectiveness of the proposed implementation. When compared to exact implementation presented in the state-of-the-art, the proposed implementation achieves a reduction in power consumption by up to 49% with a speedup of 3.2×. Moreover, the hardware resources are reduced by 40% while consuming 82% less energy in classifying an input touch with an accuracy loss less than 5%.

The reliability of digital images when used to assess burn wounds

2003 ◽  
Vol 9 (1_suppl) ◽  
pp. 22-24 ◽  
Author(s):  
O C Jones ◽  
D I Wilson ◽  
S Andrews
Keyword(s):  
Image Quality ◽  
Digital Image ◽  
Digital Images ◽  
Burn Wounds ◽  
Partial Thickness ◽  
Partial Thickness Burns ◽  
Burn Depth ◽  
Better Than ◽  
Good Agreement ◽  
Made In

summary Sixty burn wounds were assessed in person. The same observer later assessed them using digital images of different sizes. The file sizes tested were 2.25, 5.5 and 9 MByte per image. There was good agreement between the diagnoses of burn depth made using the digital images and those made in person, with kappa scores of 0.53–0.60. There were no major differences between the three file sizes. The assessments made of the partial-thickness burns showed a lower rate of agreement between the in-person and the digital image assessments and for these burns the 2.25 MByte images were apparently as good or better than the larger images. There was little difference between the three file sizes in terms of observer confidence, usefulness of the location shot, or perceived image quality. There was no significant advantage in using larger file sizes to assess burn wounds.

scholarly journals A New Method for Recognizing Cytokines Based on Feature Combination and a Support Vector Machine Classifier

Molecules ◽  
2018 ◽  
Vol 23 (8) ◽  
pp. 2008 ◽  
Author(s):  
Zhe Yang ◽  
Juan Wang ◽  
Zhida Zheng ◽  
Xin Bai
Keyword(s):  
Support Vector Machine Classifier ◽  
New Method ◽  
Evolutionary Information ◽  
Support Vector ◽  
Feature Combination ◽  
Medical Field ◽  
Low Sensitivity ◽  
Matthew’S Correlation Coefficient ◽  
Sensitivity Specificity ◽  
Better Than

Research on cytokine recognition is of great significance in the medical field due to the fact cytokines benefit the diagnosis and treatment of diseases, but the current methods for cytokine recognition have many shortcomings, such as low sensitivity and low F-score. Therefore, this paper proposes a new method on the basis of feature combination. The features are extracted from compositions of amino acids, physicochemical properties, secondary structures, and evolutionary information. The classifier used in this paper is SVM. Experiments show that our method is better than other methods in terms of accuracy, sensitivity, specificity, F-score and Matthew’s correlation coefficient.

Comparison of Processing Chains Based on Support Vector Machine Classifier for Hyperspectral Image Classification

2012 ◽  
Vol 433-440 ◽  
pp. 646-649
Author(s):  
Jee Cheng Wu ◽  
Bo Kai Lin ◽  
Gwo Chyang Tsuei
Keyword(s):  
Support Vector Machine ◽  
Support Vector Machine Classifier ◽  
Hyperspectral Image ◽  
Test Sample ◽  
Support Vector ◽  
Feature Transformation ◽  
Hyperspectral Image Classification ◽  
Transformation Methods ◽  
Noise Fraction ◽  
Better Than

In this research, we compared the performance of different processing chains resulting from combinations of spatial denoising filters, unsupervised feature transformation methods, and a support vector machine classifier. Two different training and test sample scenarios were investigated and conducted on an AVIRIS image over the Indian Pines region in Indiana, USA. The results showed that by using the process chain (adaptive enhanced Lee filter, maximum noise fraction, and support vector machine) the classification accuracies of the kappa coefficient were better than those of the best previously published techniques.

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