Performance Analysis of MIA Algorithm for LDPC Codes in near Space Rain Attenuation Channel

2011 ◽  
Vol 148-149 ◽  
pp. 1576-1582
Author(s):  
Yi Dong Su ◽  
Shu Xin Chen ◽  
Hao Wu
Keyword(s):  
Iterative Decoding ◽  
High Performance ◽  
Channel Model ◽  
Ldpc Codes ◽  
Low Complexity ◽  
Rain Attenuation ◽  
Soft Decision ◽  
Decision Algorithm ◽  
Decoding Complexity ◽  
Near Space

According to the influence of grand reflector to the channel, near space Ka-band rain attenuation channel model of area coverage is improved. According to RRWBF algorithm and UMP BP-Based algorithm of LDPC codes, a mixed iterative decoding algorithm is proposed. The algorithm takes advantage of low complexity of hard-decision algorithm and high performance of soft-decision algorithm, so in near space rain attenuation channel, the decoding complexity significantly reduced when bit error rate performance does not decline. Simulation results show that in near space rain attenuation channel, MIA algorithm can reduce decoding complexity by about 30%, compare with the UMP BP-Based algorithm.

scholarly journals High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes

Symmetry ◽  
2021 ◽  
Vol 13 (4) ◽  
pp. 700
Author(s):  
Yufei Zhu ◽  
Zuocheng Xing ◽  
Zerun Li ◽  
Yang Zhang ◽  
Yifan Hu
Keyword(s):  
High Performance ◽  
Ldpc Codes ◽  
Low Complexity ◽  
Cmos Technology ◽  
Area Efficiency ◽  
Prior Art ◽  
New Radio ◽  
High Area ◽  
Significant Area ◽  
Area Efficient

This paper presents a novel parallel quasi-cyclic low-density parity-check (QC-LDPC) encoding algorithm with low complexity, which is compatible with the 5th generation (5G) new radio (NR). Basing on the algorithm, we propose a high area-efficient parallel encoder with compatible architecture. The proposed encoder has the advantages of parallel encoding and pipelined operations. Furthermore, it is designed as a configurable encoding structure, which is fully compatible with different base graphs of 5G LDPC. Thus, the encoder architecture has flexible adaptability for various 5G LDPC codes. The proposed encoder was synthesized in a 65 nm CMOS technology. According to the encoder architecture, we implemented nine encoders for distributed lifting sizes of two base graphs. The eperimental results show that the encoder has high performance and significant area-efficiency, which is better than related prior art. This work includes a whole set of encoding algorithm and the compatible encoders, which are fully compatible with different base graphs of 5G LDPC codes. Therefore, it has more flexible adaptability for various 5G application scenarios.

scholarly journals A Construction of High Performance Quasicyclic LDPC Codes: A Combinatoric Design Approach

2019 ◽  
Vol 2019 ◽  
pp. 1-10 ◽  
Author(s):  
Muhammad Asif ◽  
Wuyang Zhou ◽  
Muhammad Ajmal ◽  
Zain ul Abiden Akhtar ◽  
Nauman Ali Khan
Keyword(s):  
Iterative Decoding ◽  
High Performance ◽  
Linear Complexity ◽  
Signal To Noise Ratio ◽  
Additive White Gaussian Noise ◽  
Ldpc Codes ◽  
Combinatorial Designs ◽  
Parity Check ◽  
Excellent Performance ◽  
Moderate Length

This correspondence presents a construction of quasicyclic (QC) low-density parity-check (LDPC) codes based on a special type of combinatorial designs known as block disjoint difference families (BDDFs). The proposed construction of QC-LDPC codes gives parity-check matrices with column weight three and Tanner graphs having a girth lower-bounded by 6. The proposed QC-LDPC codes provide an excellent performance with iterative decoding over an additive white Gaussian-noise (AWGN) channel. Performance analysis shows that the proposed short and moderate length QC-LDPC codes perform as well as their competitors in the lower signal-to-noise ratio (SNR) region but outperform in the higher SNR region. Also, the codes constructed are quasicyclic in nature, so the encoding can be done with simple shift-register circuits with linear complexity.

A Min-Sum Algorithm Suitable for Hardware Implementation Based on LDPC Codes

2011 ◽  
Vol 271-273 ◽  
pp. 458-463
Author(s):  
Rui Ping Chen ◽  
Zhong Xun Wang ◽  
Xin Qiao Yu
Keyword(s):  
Hardware Implementation ◽  
Ldpc Codes ◽  
Low Complexity ◽  
Scaling Factor ◽  
Computation Complexity ◽  
Decoding Complexity ◽  
Decoding Algorithms ◽  
Hardware Resource ◽  
Simulation Results ◽  
Ber Performance

Decoding algorithms with strong practical value not only have good decoding performance, but also have the computation complexity as low as possible. For this purpose, the paper points out the modified min-sum decoding algorithm(M-MSA). On the condition of no increasing in the decoding complexity, it makes the error-correcting performance improved by adding the appropriate scaling factor based on the min-sum algorithm(MSA), and it is very suitable for hardware implementation. Simulation results show that this algorithm has good BER performance, low complexity and low hardware resource utilization, and it would be well applied in the future.

Low Complexity Weighted Reliability-Based Iterative Decoding of LDPC Codes

2012 ◽  
Vol E95.B (11) ◽  
pp. 3572-3575 ◽  
Author(s):  
Zhiliang HUANG ◽  
Ming CHEN ◽  
Chunjuan DIAO ◽  
Jiamin LI
Keyword(s):  
Iterative Decoding ◽  
Ldpc Codes ◽  
Low Complexity

Low-complexity soft-decision parallel equaliser algorithms for Chinese next-generation-high-performance AV

2016 ◽  
Vol 23 (3) ◽  
pp. 119-129
Author(s):  
Daoping Jiang ◽  
Zhaofeng Zhang ◽  
Ge Gao ◽  
Jianmin Zhuang ◽  
Runsheng He
Keyword(s):  
High Performance ◽  
Low Complexity ◽  
Next Generation ◽  
Soft Decision

scholarly journals Iterative Decoding of LDPC-Based Product Codes and FPGA-Based Performance Evaluation

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 122
Author(s):  
Weigang Chen ◽  
Wenting Zhao ◽  
Hui Li ◽  
Suolei Dai ◽  
Changcai Han ◽  
...  
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Iterative Decoding ◽  
Ldpc Codes ◽  
Low Complexity ◽  
High Rate ◽  
Error Floor ◽  
Product Codes ◽  
Field Programmable ◽  
Implementation Costs

Low-density parity-check (LDPC) codes have the potential for applications in future high throughput optical communications due to their significant error correction capability and the parallel decoding. However, they are not able to satisfy the very low bit error rate (BER) requirement due to the error floor phenomenon. In this paper, we propose a low-complexity iterative decoding scheme for product codes consisting of very high rate outer codes and LDPC codes. The outer codes aim at eliminating the residual error floor of LDPC codes with quite low implementation costs. Furthermore, considering the long simulation time of computer simulation for evaluating very low BER, the hardware platform is built to accelerate the evaluation of the proposed iterative decoding methods. Simultaneously, the fixed-point effects of the decoding algorithms are also be evaluated. The experimental results show that the iterative decoding of the product codes can achieve a quite low bit error rate. The evaluation using field programmable gate array (FPGA) also proves that product codes with LDPC codes and high-rate algebraic codes can achieve a good trade-off between complexity and throughput.

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