The Design of Insulator Leakage Current Monitoring Device Based on MSP430 Microcontroller

2012 ◽  
Vol 263-266 ◽  
pp. 485-490
Author(s):  
Dan Zhong ◽  
Jian Xun Hu ◽  
Wen Fang Ding ◽  
Hui Chen
Keyword(s):  
Low Power ◽  
Transmission Line ◽  
Current Pulse ◽  
Leakage Current ◽  
Controller Design ◽  
High Reliability ◽  
Pulse Frequency ◽  
Monitoring Device ◽  
Ultra Low Power ◽  
Current Monitoring

This article describes a transmission line insulator leakage current monitoring device, the device is based on the MSP430 ultra low power mixed signal controller design, both the transmission line insulator leakage current rms leakage current pulse, the leakage current pulse frequency and ambient humidity characteristic quantities to be monitored, with low power consumption, high reliability.

Ultra-Low Power Stress Sensing By Leakage Current of P-N Junctions

2020 ◽  
Author(s):  
Zhiqiang Feng ◽  
Xuefeng He ◽  
Junru Li ◽  
Shen Li ◽  
Zhengguo Shang
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
Ultra Low Power ◽  
Stress Sensing

A 28 nm full-margin, high-reliability, and ultra-low-power consumption sense amplifier for STT-MRAM

2019 ◽  
Vol 100-101 ◽  
pp. 113465
Author(s):  
S.W. Zheng ◽  
J.S. Bi ◽  
K. Xi ◽  
J. Liu ◽  
M. Liu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Reliability ◽  
Low Power Consumption ◽  
Ultra Low Power ◽  
Sense Amplifier

scholarly journals Design of FinFET based 128 bit SRAM in 7nm & Various Effects near Threshold Operation for Ultra Low Power Application.

2020 ◽  
Vol 8 (5) ◽  
pp. 3361-3366
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
High Performance ◽  
Research Work ◽  
Threshold Region ◽  
Ultra Low Power ◽  
Pvt Variations ◽  
Power Application ◽  
Subthreshold Operation ◽  
Near Threshold

With the existing technology and survey it indicates the increasing the number of transistors count and exploring methodologies leads to innovative design in memories. In general SRAM occupies considerable amount of area and less performance due to leakage power that limits the operation under sub threshold region. The power consumption of the circuit design is primarily depends on the switching activity of the transistor that leads to increasing of leakage current at near or subthreshold operation. Some of the challenges like PVT variations, SEU, SEE, and RDF lead to reduction in performance, increasing the power, BTI, sizing, delay and yield. The research work in this paper primarily describes the challenges with the technology and effects on CMOS & Finfet designs. The second aspect of the paper is to represents the design methodologies of CMOS & FinFET models and its operation. The third part of the paper explains design tradeoff of FinFET SRAM. Final sections present a comparison of high performance, low power at normal and near threshold operation. The Comparisons is made on the basis of process parameters and made a conclusion with circuit functionality, reliability under different technologies. FinFET based SRAM’s are the emerging memory trends by the performance under or near sub-threshold operation with the minimal variation in the leakage current, minimal gate delay is an alternate solution to the traditional CMOS memory designs as showed in the present work.

scholarly journals Low Leakage Current Symmetrical Dual-k 7 nm Trigate Bulk Underlap FinFET for Ultra Low Power Applications

IEEE Access ◽  
2019 ◽  
Vol 7 ◽  
pp. 17256-17262 ◽  
Author(s):  
Mahmoud S. Badran ◽  
Hanady Hussein Issa ◽  
Saleh M. Eisa ◽  
Hani Fikry Ragai
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
Ultra Low Power ◽  
Low Leakage ◽  
Low Leakage Current

Development of leakage current monitoring device for arrester

2016 ◽  
Author(s):  
Yusuke Takido ◽  
Sho Mochizuki ◽  
Yuichi Takahashi ◽  
Koji Ajiki ◽  
Tomohiro Owaku ◽  
...  
Keyword(s):  
Leakage Current ◽  
Monitoring Device ◽  
Current Monitoring
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