Implementation of CRC by Using FPGA in Data Communication

2013 ◽  
Vol 325-326 ◽  
pp. 1805-1808
Author(s):  
Lie Wang ◽  
Yi Jie Wang
Keyword(s):  
Hardware Implementation ◽  
Data Communication ◽  
Communication Process ◽  
Hardware Description Language ◽  
Verilog Hdl ◽  
Description Language ◽  
Communication Structure ◽  
Development Platform ◽  
Hardware Description ◽  
Analyze Data

By introducing the basic principle of ordinary CRC algorithm, the paper develops an algorithm which can be used to analyze data communication structure and construct design process. At the same time, it can be quickly implemented in the data communication process. The algorithm uses Verilog HDL hardware description language to complete all the design on ISE development platform. And it uses Xilinxs development board Virtex-II Pro to achieve the final realization. Compared with traditional methods, the algorithm is simple and intuitive, which reduces computational the delays and saves space. It also benefits hardware implementation.

scholarly journals Design and Analysis of Radix-8/4/2 64b/32b Integer Divider Using COMPASS Cell Library

VLSI Design ◽  
2000 ◽  
Vol 11 (4) ◽  
pp. 331-338 ◽  
Author(s):  
Chua-Chin Wang ◽  
Chenn-Jung Huang ◽  
I-Yen Chang
Keyword(s):  
High Speed ◽  
Hardware Description Language ◽  
Verilog Hdl ◽  
Description Language ◽  
Throughput Rate ◽  
Cell Library ◽  
Conversion Algorithm ◽  
Hardware Description ◽  
Simulation Results

A high speed 64b/32b integer divider employing digit-recurrence division method and the on-the-fly conversion algorithm, wherein a fast normalizer is included, which is used as the pre-processor of the proposed integer divider. For the sake of enhancing throughput rate, the proposed divider uses a mixed radix-8/4/2 division instead of the traditional radix-2 division. On-the-fly remainder adjustment is also realized in the converter module of the divider. The entire design is written in Verilog HDL (hardware description language) employing COMPASS 0.6 μm 1P3M cell library (V3.0), and then synthesized by SYNOPSYS. The simulation results indicate that our design is a better option than the existing long divider designs.

scholarly journals Simple Hardware Implementation of Motion Estimation Algorithms

2019 ◽  
Vol 11 (3) ◽  
Author(s):  
Juan Romero ◽  
Damien Verdier ◽  
Clement Raffaitin ◽  
Luis Miguel Procel ◽  
Lionel Trojman
Keyword(s):  
Optical Flow ◽  
Field Programmable Gate Array ◽  
Hardware Implementation ◽  
Software Implementation ◽  
Hardware Description Language ◽  
Successful Implementation ◽  
Description Language ◽  
Estimation Algorithms ◽  
Field Programmable ◽  
Hardware Description

We present in the following work a hardware implementation of the two principal optical flow methods. The work is based on the methods developed by Lucas & Kanade, and Horn & Schunck. The implementation is made by using a field programmable gate array and Hardware Description Language. To achieve a successful implementation, the algorithms were optimized. The results show the optical flow as a vector field over one frame, which enable an easy detection of the movement. The results are compared to a software implementation to insure the success of the method. The implementation is a fast implementation capable of quickly overcoming a traditional implementation in software.

IP Core Design of 8253 Based on Quartus II

2013 ◽  
Vol 380-384 ◽  
pp. 2941-2944
Author(s):  
Hai Yan Zhang
Keyword(s):  
Software Development ◽  
Hardware Description Language ◽  
Logic Design ◽  
Ip Core ◽  
Description Language ◽  
Development Platform ◽  
Quartus Ii ◽  
Hardware Description ◽  
Gate Array

Provided by ALTERA FPGA/CPLD Quartus II development software development platform. programmable timer/counter 8253s functions and internal circuitry as the basis, combined with programmable gate array (FPGA) products FLEX10KE characteristics, using VHDL hardware description language and schematic Figure two ways 8253 for hierarchical, modular, parameterized logic design. The completed design will be configured to the chip of FLEX10KE,and Proved to be correct.

scholarly journals Study of Data Security Algorithms using Verilog HDL

2015 ◽  
Vol 5 (5) ◽  
pp. 1092
Author(s):  
M. Sumathi ◽  
D. Nirmala ◽  
R. Immanuel Rajkumar
Keyword(s):  
Performance Evaluation ◽  
Data Security ◽  
Hardware Description Language ◽  
Performance Study ◽  
Verilog Hdl ◽  
Description Language ◽  
Quartus Ii ◽  
Encryption And Decryption ◽  
Different Types ◽  
Hardware Description

This paper describes an overview of data security algorithms and its performance evaluation. AES, RC5 and SHA algorithms have been taken under this study. Three different types of security algorithms used to analyze the performance study. The designs were implemented in Quartus-II software. The results obtained for encryption and decryption procedures show a significant improvement on the performance of the three algorithms. In this paper, 128-bit AES, 64-bit of RC5 and 512-bit of SHA256 encryption and Decryption has been made using Verilog Hardware Description Language and simulated using ModelSim.

scholarly journals Compact Hardware Architectures of Enocoro-128v2 Stream Cipher for Constrained Embedded Devices

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1505
Author(s):  
Lampros Pyrgas ◽  
Paris Kitsos
Keyword(s):  
Hardware Implementation ◽  
Stream Cipher ◽  
Hardware Description Language ◽  
Description Language ◽  
Embedded Devices ◽  
Lightweight Cryptography ◽  
Hardware Architectures ◽  
Hardware Description ◽  
First Time ◽  
Constrained Devices

Lightweight cryptography is a vital and fast growing field in today’s world where billions of constrained devices interact with each other. In this paper, two novel compact architectures of the Enocoro-128v2 stream cipher are presented. The Enocoro-128v2 is part of the ISO/IEC 29192-3 standard. The first architecture has an 8-bit datapath while the second one has a 4-bit datapath. The proposed architectures were implemented on the BASYS3 board (Artix 7 XC7A35T) using the VERILOG hardware description language. The hardware implementation of the proposed 8-bit architecture runs at a 189 MHz clock and reaches a throughput equal to 302 Mbps, while at the same time, it utilizes only 254 Look-up Tables (LUTs) and 330 Flip-flops (FFs). Each round of computations requires 5 clock cycles. The 4-bit implementation has an operating frequency of 204 MHz and reaches a throughput equal to 181 Mbps, with each round requiring 9 clock cycles. The 4-bit implementation utilizes 249 LUTs and 343 FFs. To our knowledge, this is the first time that such implementations of the Enocoro-128v2 are presented. Both implementations utilize a very low number of resources (only 78 FPGA slices are required for the 8-bit architecture and only 83 for the 4-bit one) and the results demonstrate that they are sustainable for area constrained embedded devices.

Design of AD Controller Customized IP Core Based on FPGA

2015 ◽  
Vol 727-728 ◽  
pp. 859-862
Author(s):  
Xiang Sheng Huang
Keyword(s):  
Experimental Results ◽  
Hardware Description Language ◽  
Ip Core ◽  
Verilog Hdl ◽  
Description Language ◽  
C Language ◽  
The Core ◽  
Hardware Description ◽  
Program Interface ◽  
And Control

This design elaborates thedevelopment process of the custom IP core AD9280 controller based on FPGA. Thedesign uses FPGA as the core of the microcontroller, realizes the function ofAD controller by adopting the hardware description language,Verilog HDL and encapsulates it to the custom IP core in the SOPCBuilder. In the NIOS II, the application program interface (API) function ofthe AD controller software is used to access and control the hardware, thesoftware is written by using C language. The experimental results show thatthis custom IP core is feasible and flexible, fully reflects the advantages ofSOPC technology.

Design and Implementation of Reconfigurable Encryption and Decryption System Based on SOPC

2013 ◽  
Vol 347-350 ◽  
pp. 2979-2982
Author(s):  
Qing Fang Zhou ◽  
Qian Huang ◽  
Ying Yuan ◽  
Jun Yang
Keyword(s):  
Hardware Description Language ◽  
Ip Core ◽  
Verilog Hdl ◽  
Description Language ◽  
Nios Ii ◽  
Design And Implementation ◽  
Network Controller ◽  
Encryption And Decryption ◽  
Hardware Description ◽  
Encryption Decryption

The system is based on DES/3DES, AES cipher algorithm as the research object.According to the characteristics of the algorithm, designs a configuration mode which can share resource in space and configurate algorithm in time. Then it uses hardware description language Verilog HDL to realize and optimize the design, and completes a custom reconfigurable DES/3DES/AES encryption/decryption IP core. By SOPC technology, the IP core, Nios II processor, network controller and other function. The design hardware structureis simple, flexibility, security, which can be widely used in the field of informationsecurity.

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