I2C and HSTL IO Standard Based Low Power Thermal Aware Adder Design on 45nm FPGA

2015 ◽  
Vol 1098 ◽  
pp. 31-36 ◽  
Author(s):  
Kartik Kalia ◽  
Khyati Nanda ◽  
Arushi Aggarwal ◽  
Akshita Goel ◽  
Shivani Malhotra

In this work, we are we are going to search the most thermal and energy efficient IO Standards among the HSTL family and I2C family on 45 nm technology based FPGA. Here we are also doing thermal analysis for 273.15K-343.15K temperature, while during comparing the different IO Standards, we are taking the improvement level at 283.15K. In leakage power analysis, we are getting 9.09% improvement in HSTL with respect to others and in IO power analysis I2C shows 57.89% improvement with respect to others. In thermal analysis for maximum ambient temperature, we observe 1.79% improvement in HSTL_II as compared to others and in Junction Temperature analysis HSTL_I and I2C are 3.6% efficient than others. HSTL_I has minimum Theta Junction to Ambient Temperature value. In this work, we are using 45nm Spartan-6 FPGA. . We are taking airflow of 250LFM where LFM is a unit of airflow. LFM is linear feet per minute. Adder is our target design.

2015 ◽  
Vol 1098 ◽  
pp. 37-43
Author(s):  
Kartik Kalia ◽  
Khyati Nanda ◽  
Arushi Aggarwal ◽  
Akshita Goel ◽  
Shivani Malhotra

In this work, we are going to search the most thermal and energy efficient technology among 90nm, 65nm, 45nm, 40nm and 38nm technology based FPGA, and also searching the most thermal and energy efficient airflow, and heat sink profile. We are also doing thermal analysis for 273.15K-343.15K temperature. we are getting 31.67%, 75.71%, reduction in leakage power for 250LFM and 58.53%, 75.71% reduction in leakage power for 500LFM when we scale down ambient temperature from 343.15K to 283.15K for 65nm, 28nm technology based FPGA. There is 84.54%, 85.65%, reduction in junction temperature for 250LFM, 84.90%, 85.65%, reduction in junction temperature for 500LFM when we scale down ambient temperature from 343.15K to 283.15K for 65nm, 28nm technology based FPGA. In this work, we are using 90nm Spartan-3E FPGA, 65nm Virtex-5 FPGA, 45nm Spartan-6 FPGA, 40nm Virtex-6 FPGA, and 28nm Artix-7 FPGA. We are taking two different airflow of 250LFM and 500LFM. LFM is a unit of airflow. LFM is linear feet per minute. Adder is our target design.


2014 ◽  
Vol 612 ◽  
pp. 65-70 ◽  
Author(s):  
Bishwajeet Pandey ◽  
Tanesh Kumar ◽  
Teerath Das ◽  
S.M.M. Islam ◽  
Jagdish Kumar

Thermal mechanism cover the mechanics of Hit Sink, Airflow mechanics, and Ambient Temperature Mechanism to reduce junction temperature in design of Finite Duration Impulse Response (FIR) Filter. In this work, we are implementing FIR Filter on 28nm FPGA. After implementation of FIR Filter, we analyze the effect of in-built mechanism of Air Flow Controller and their produced Airflow on the junction temperature of FPGA. The mechanism of Ambient Temperature controller also play significant role in leakage power dissipation as well as junction temperature of FPGA. Finally, the mechanical structure of Hit Sink is considered for control of junction temperature of FPGA. There is 73.38% reduction in Leakage Power on 55 C ambient temperature when we increase airflow from 250 LFM to 500 LFM. Along with 500 LFM airflow, if we provide high profile hit sink then there is 78.31% reduction in leakage power. There is 37.68% reduction in junction temperature of FPGA when we increase airflow from 250LFM to 500LFM. Along with 500 LFM airflow, if we provide high profile hit sink then there is 41.76 % reduction in junction temperature on 45C ambient temperature. There is no effect of airflow on clock power. Whereas there is significant reduction in Logic Power, Signal Power, DSPs Power and IOs Power with change in Airflow.


2018 ◽  
Vol 35 (1) ◽  
pp. 1-11 ◽  
Author(s):  
Muna E. Raypah ◽  
Dheepan M.K. ◽  
Mutharasu Devarajan ◽  
Shanmugan Subramani ◽  
Fauziah Sulaiman

Purpose Thermal behavior of light-emitting diode (LED) device under different operating conditions must be known to enhance its reliability and efficiency in various applications. The purpose of this study is to report the influence of input current and ambient temperature on thermal resistance of InGaAlP low-power surface-mount device (SMD) LED. Design/methodology/approach Thermal parameters of the LED were measured using thermal transient measurement via Thermal Transient Tester (T3Ster). The experimental results were validated using computational fluid dynamics (CFD) software. Findings As input current increases from 50 to 90 mA at 25°C, the relative increase in LED package (ΔRthJS) and total thermal resistance (ΔRthJA) is about 10 and 4 per cent, respectively. In addition, at 50 mA and ambient temperature from 25 to 65°C, the ΔRthJS and ΔRthJA are roughly 28 and 22 per cent, respectively. A good agreement between simulation and experiment results of junction temperature. Originality/value Most of previous studies have focused on thermal management of high-power LEDs. There were no studies on thermal analysis of low-power SMD LED so far. This work will help in predicting the thermal performance of low-power LEDs in solid-state lighting applications.


In this research work, a low power transceiver is designed using Spartan-3 and Spartan-6 Field-Programmable Gate Array (FPGA). In this work, a Universal Asynchronous Receiver Transmitter (UART) device is used as a transceiver. The implementation of UART is possible with EDA tools called Xilinx 14.1 and the results of the power analysis are targeted on Spartan-3 and Spartan-6 FPGA. The variation of different power of chips that are fabricated on FPGA for e.g., Input/Output (I/O) power consumption, Leakage power dissipation, Signal power utilization, Logic power usage, and the use of Total power, is observed by changing the voltage supply. This research work shows how the change in voltage influence the power consumption of UART on Spartan-3 and Spartan-6 FPGA devices. It is observed that Spartan-6 is found to be more powerefficient as voltage supply increases.


2014 ◽  
Vol 1082 ◽  
pp. 467-470
Author(s):  
Rishita Saini ◽  
Neha Bansal ◽  
Meenakshi Bansal ◽  
Lakshay Kalra ◽  
Preet Mohan Singh ◽  
...  

—Thermal aware design is currently gaining importance in VLSI research domain. In this work, we are going to design thermal aware energy efficient ROM on Virtex-5 FPGA. Ambient Temperature, airflow, and heat sink profile play a significant role in thermal aware hardware design life cycle. Ambient temperature is a temperature of surroundings. Airflow is measured in Linear Feet per Minute (LFM). Medium profile and high profile are two different heat sink profile available in XPower analyzer.When frequency goes from 4.0GHz to 1.0GHz, there is 21.8% reduction in clock power, 75% reduction in I/O Power, 35.6% reduction in leakage power and 53.8% reduction in total power at the same frequency.


2014 ◽  
Vol 2014 ◽  
pp. 1-6
Author(s):  
P. F. Khaleelur Rahiman ◽  
V. S. Jayanthi

Cochlea devices are powered up with the help of batteries and they should possess long working life to avoid replacing of devices at regular interval of years. Hence the devices with low power consumptions are required. In cochlea devices there are numerous filters, each responsible for frequency variant signals, which helps in identifying speech signals of different audible range. In this paper, multiplierless lookup table (LUT) based auditory filter is implemented. Power aware adder architectures are utilized to add the output samples of the LUT, available at every clock cycle. The design is developed and modeled using Verilog HDL, simulated using Mentor Graphics Model-Sim Simulator, and synthesized using Synopsys Design Compiler tool. The design was mapped to TSMC 65 nm technological node. The standard ASIC design methodology has been adapted to carry out the power analysis. The proposed FIR filter architecture has reduced the leakage power by 15% and increased its performance by 2.76%.


In this research work, a low power transceiver is designed using Spartan-3 and Spartan-6 Field-Programmable Gate Array (FPGA). In this work, a Universal Asynchronous Receiver Transmitter (UART) device is used as a transceiver. The implementation of UART is possible with EDA tools called Xilinx 14.1 and the results of the power analysis are targeted on Spartan-3 and Spartan-6 FPGA. The variation of different power of chips that are fabricated on FPGA for e.g., Input/Output (I/O) power consumption, Leakage power dissipation, Signal power utilization, Logic power usage, and the use of Total power, is observed by changing the voltage supply. This research work shows how the change in voltage influence the power consumption of UART on Spartan-3 and Spartan-6 FPGA devices. It is observed that Spartan-6 is found to be more powerefficient as voltage supply increases.


Electronics ◽  
2021 ◽  
Vol 10 (11) ◽  
pp. 1291
Author(s):  
Giuseppe Schirripa Schirripa Spagnolo ◽  
Fabio Leccese

Nowadays, signal lights are made using light-emitting diode arrays (LEDs). These devices are extremely energy efficient and have a very long lifetime. Unfortunately, especially for yellow/amber LEDs, the intensity of the light is closely related to the junction temperature. This makes it difficult to design signal lights to be used in naval, road, railway, and aeronautical sectors, capable of fully respecting national and international regulations. Furthermore, the limitations prescribed by the standards must be respected in a wide range of temperature variations. In other words, in the signaling apparatuses, a system that varies the light intensity emitted according to the operating temperature is useful/necessary. In this paper, we propose a simple and effective solution. In order to adjust the intensity of the light emitted by the LEDs, we use an LED identical to those used to emit light as a temperature sensor. The proposed system was created and tested in the laboratory. As the same device as the ones to be controlled is used as the temperature sensor, the system is very stable and easy to set up.


2021 ◽  
Vol 1084 (1) ◽  
pp. 012120
Author(s):  
M Srinivasan ◽  
P Manojkumar ◽  
A Dheepancharavarthy

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