Design of LDPC Decoder Based on CMMB

2012 ◽  
Vol 588-589 ◽  
pp. 785-789
Author(s):  
Jun Wang ◽  
Jing He ◽  
Xin Yu Xu
Keyword(s):  
Parallel Architecture ◽  
Design Parameters ◽  
Point Model ◽  
Data Format ◽  
Initial Information ◽  
Ldpc Decoder ◽  
Decoding Algorithms ◽  
Intermediate Data ◽  
Ldpc Decoding ◽  
Optimal Decoding

In this paper, design of a LDPC decoder in CMMB is presented. LDPC decoding algorithms for CMMB are analyzed and the optimal decoding algorithm-Normalized MSA are used to implement the decoder, and the algorithm is simulated to determine the design parameters. A partial parallel architecture based on Normalized MSA algorithm is proposed, and the architecture is simulated with a fixed-point model to determine the best quantification scheme for initial information and intermediate data format.

scholarly journals Fully Parallel Architecture of QC-LDPC Decoder for IEEE 802.11n Application

2020 ◽  
Vol 9 (1) ◽  
pp. 1726-1731
Keyword(s):  
Error Correction ◽  
Message Passing ◽  
Iterative Algorithms ◽  
Parallel Architecture ◽  
Block Size ◽  
Ldpc Code ◽  
Ieee 802.11N ◽  
Ldpc Decoder ◽  
Ldpc Decoding ◽  
Finite State

A Low density parity check (LDPC) code, have become most accepted error correction code for efficient and reliable communication due to a good performance. The VLSI implementation of LDPC decoder is a big challenge. Iterative message passing decoding algorithms propose excellent error correction performance but a large decoding complexity for different code lengths and code rates. The LDPC codes decoder also faced many difficulties such as small chip areas , reduced interconnect complexities, lower power dissipation. In this paper, the design of the of Quasi Cyclic(QC)LDPC decoder for the IEEE 802.11n standard with 1/2 code rate, 648coward length and sub-block size z =27 have been designed. Initially different iterative algorithms for LDPC decoding are discussed. The Fully parallel architecture of the LDPC decoder for IEEE 802.11n standard using Min Sum decoding algorithm (MSA)has been designed. Further, the design Quasi Cyclic(QC) LDPC decoder for IEEE 802.11n have been modified by using a Finite State Machine (FSM) to control the complete decoding process.

scholarly journals Design Space of Flexible Multigigabit LDPC Decoders

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-10 ◽  
Author(s):  
Philipp Schläfer ◽  
Christian Weis ◽  
Norbert Wehn ◽  
Matthias Alles
Keyword(s):  
Design Space ◽  
State Of The Art ◽  
Cmos Technology ◽  
Systematic Investigation ◽  
Design Parameters ◽  
Ldpc Decoder ◽  
The Past ◽  
Ieee 802.11Ad ◽  
Decoder Design ◽  
First Time

Multigigabit LDPC decoders are demanded by standards like IEEE 802.15.3c and IEEE 802.11ad. To achieve the high throughput while supporting the needed flexibility, sophisticated architectures are mandatory. This paper comprehensively presents the design space for flexible multigigabit LDPC applications for the first time. The influence of various design parameters on the hardware is investigated in depth. Two new decoder architectures in a 65 nm CMOS technology are presented to further explore the design space. In the past, the memory domination was the bottleneck for throughputs of up to 1 Gbit/s. Our systematic investigation of column- versus row-based partially parallel decoders shows that this is no more a bottleneck for multigigabit architectures. The evolutionary progress in flexible multigigabit LDPC decoder design is highlighted in an extensive comparison of state-of-the-art decoders.

scholarly journals LDPC Decoder Design Using Compensation Scheme of Group Comparison for 5G Communication Systems

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 2010
Author(s):  
Chen-Hung Lin ◽  
Chen-Xuan Wang ◽  
Cheng-Kai Lu
Keyword(s):  
Communication Systems ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Compensation Scheme ◽  
Dual Mode ◽  
Ldpc Decoder ◽  
Performance Loss ◽  
Ldpc Decoding ◽  
5G Communication

This paper presents a dual-mode low-density parity-check (LDPC) decoding architecture that has excellent error-correcting capability and a high parallelism design for fifth-generation (5G) new-radio (NR) applications. We adopted a high parallelism design using a layered decoding schedule to meet the high throughput requirement of 5G NR systems. Although the increase in parallelism can efficiently enhance the throughput, the hardware implementation required to support high parallelism is a significant hardware burden. To efficiently reduce the hardware burden, we used a grouping search rather than a sorter, which was used in the minimum finder with decoding performance loss. Additionally, we proposed a compensation scheme to improve the decoding performance loss by revising the probabilistic second minimum of a grouping search. The post-layout implementation of the proposed dual-mode LDPC decoder is based on the Taiwan Semiconductor Manufacturing Company (TSMC) 40 nm complementary metal-oxide-semiconductor (CMOS) technology, using a compensation scheme of grouping comparison for 5G communication systems with a working frequency of 294.1 MHz. The decoding throughput achieved was at least 10.86 Gb/s without evaluating early termination, and the decoding power consumption was 313.3 mW.

scholarly journals The Intermediate Data Structure (IDS) for Longitudinal Historical Microdata, version 4

2014 ◽  
Vol 1 ◽  
pp. 1-26
Author(s):  
George Alter ◽  
Kees Mandemakers
Keyword(s):  
Data Structure ◽  
Social Research ◽  
Geospatial Information ◽  
Data Format ◽  
Standard Data ◽  
Intermediate Data ◽  
Hierarchical Relationships ◽  
Life Courses ◽  
Historical Life

The Intermediate Data Structure (IDS) is a standard data format that has been adopted by several large longitudinal databases on historical populations. Since the publication of the first version in Historical Social Research in 2009, two improved and extended versions have been published in the Collaboratory Historical Life Courses. In this publication we present version 4 which is the latest ‘official’ standard of the IDS. Discussions with users over the last four years resulted in important changes, like the inclusion of a new table defining the hierarchical relationships among ‘contexts’, decision schemes for recording relationships, additional fields in the metadata table, rules for handling stillbirths, a reciprocal model for relationships, guidance for linking IDS data with geospatial information, and the introduction of an extended IDS for computed variables.

Parallel Architecture Manipulators for Use in Masticatory Studies

2011 ◽  
Vol 1 (4) ◽  
pp. 100-122 ◽  
Author(s):  
Madusudanan Sathia Narayanan ◽  
Srikanth Kannan ◽  
Xiaobo Zhou ◽  
Frank Mendel ◽  
Venkat Krovi
Keyword(s):  
High Speed ◽  
Parallel Architecture ◽  
General Purpose ◽  
Design Parameters ◽  
Practical Implementation ◽  
Hardware In The Loop ◽  
Test Bed ◽  
Motion Trajectories ◽  
Structural Rigidity ◽  
Simulator Test

There is considerable scientific and commercial interest in understanding the mechanics of mastication. In this paper, the authors develop quantitative engineering tools to enable this process by: (i) designing a general purpose mastication simulator test-bed based on parallel architecture manipulator, capable of producing the requisite motions and forces; and (ii) validating this simulator with a range of test-foods, undergoing various mastication cycles under controlled and monitored circumstances. Such an implementation provides a test bed to quantitatively characterize the mastication based on “chewability index”. Due to the inherent advantages of locating actuators at the base (ground) in terms of actuator efforts and structural rigidity as well as benefits of using prismatic sliders compared to revolute actuators, the 6-P-U-S system was chosen. A detailed symbolic kinematic analysis was then conducted. For the practical implementation of the test-bed, the analytical Jacobian was examined for singularities and the design was adapted to ensure singularity free operation. A comprehensive parametric study was undertaken to obtain optimal design parameters for desired workspace and end effector forces. Experiments captured jaw motion trajectories using the high speed motion capture system which served as an input to the hardware-in-the-loop simulator platform.

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