Numerical Simulation of Stretchable and Foldable Silicon Integrated Circuits

2009 ◽  
Vol 74 ◽  
pp. 197-200
Author(s):  
Zhuang Jian Liu ◽  
Yong Wei Zhang ◽  
Ji Zhou Song ◽  
Dae Hyeong Kim ◽  
Yong Gang Huang ◽  
...  
Keyword(s):  
Thin Film ◽  
Numerical Simulation ◽  
Integrated Circuits ◽  
High Performance ◽  
Large Strain ◽  
Simulation Studies ◽  
Linear Elastic ◽  
Silicon Integrated Circuits ◽  
Elastic Responses ◽  
Principal Strains

This paper presents numerical simulation strategies for stretchable silicon integrated circuits that use stiff thin film on elastomeric substrates. Detailed numerical simulation studies reveal the key underlying aspects of these systems. The results indicate, as an example, optimized mechanics and materials for circuits that exhibit maximum principal strains less than 0.2% even for applied strains of up to ~90%. Simple circuits, including CMOS inverters provide an example that validates these designs. The results suggest practical routes to high performance electronics with linear elastic responses to large strain deformations, suitable for diverse applications that are not readily addressed with conventional wafer-based technologies.

The Structure and Properties of MoSi2 Thin Film in Mos Process

1980 ◽  
Vol 38 ◽  
pp. 326-327
Author(s):  
C.K. Wu ◽  
P. Chang ◽  
N. Godinho
Keyword(s):  
Thin Film ◽  
Integrated Circuits ◽  
High Performance ◽  
Large Scale ◽  
Process Development ◽  
Structure And Properties ◽  
Metal Silicides ◽  
High Oxidation ◽  
Important Approach ◽  
High Oxidation Resistance

Recently, the use of refractory metal silicides as low resistivity, high temperature and high oxidation resistance gate materials in large scale integrated circuits (LSI) has become an important approach in advanced MOS process development (1). This research is a systematic study on the structure and properties of molybdenum silicide thin film and its applicability to high performance LSI fabrication.

scholarly journals High-Performance Top-Gate Thin-Film Transistor with an Ultra-Thin Channel Layer

Nanomaterials ◽  
2020 ◽  
Vol 10 (11) ◽  
pp. 2145 ◽  
Author(s):  
Te Jui Yen ◽  
Albert Chin ◽  
Vladimir Gritsenko
Keyword(s):  
Thin Film ◽  
Integrated Circuits ◽  
High Performance ◽  
Thin Film Transistor ◽  
Three Dimensional ◽  
Random Access ◽  
Oxide Thin Film ◽  
Amorphous Sio2 ◽  
Sio2 Substrate ◽  
Channel Layer

Metal-oxide thin-film transistors (TFTs) have been implanted for a display panel, but further mobility improvement is required for future applications. In this study, excellent performance was observed for top-gate coplanar binary SnO2 TFTs, with a high field-effect mobility (μFE) of 136 cm2/Vs, a large on-current/off-current (ION/IOFF) of 1.5 × 108, and steep subthreshold slopes of 108 mV/dec. Here, μFE represents the maximum among the top-gate TFTs made on an amorphous SiO2 substrate, with a maximum process temperature of ≤ 400 °C. In contrast to a bottom-gate device, a top-gate device is the standard structure for monolithic integrated circuits (ICs). Such a superb device integrity was achieved by using an ultra-thin SnO2 channel layer of 4.5 nm and an HfO2 gate dielectric with a 3 nm SiO2 interfacial layer between the SnO2 and HfO2. The inserted SiO2 layer is crucial for decreasing the charged defect scattering in the HfO2 and HfO2/SnO2 interfaces to increase the mobility. Such high μFE, large ION, and low IOFF top-gate SnO2 devices with a coplanar structure are important for display, dynamic random-access memory, and monolithic three-dimensional ICs.

Numerical Simulation of Nc-Silicon PIN Solar Cells with AMPS-1D

2013 ◽  
Vol 712-715 ◽  
pp. 309-312 ◽  
Author(s):  
Ming Kun Xu
Keyword(s):  
Thin Film ◽  
Numerical Simulation ◽  
Solar Cells ◽  
Solar Cell ◽  
Conversion Efficiency ◽  
Thin Film Solar Cell ◽  
High Performance ◽  
Fill Factor ◽  
High Efficiency ◽  
Program Package

P+a-SiC/ I nc-Si/N+a-Si structure solar cells is simulated by AMPS-1D program package to characterize the new thin film solar cell. In order to analyze the characteristics of the device, the thickness of layer are considered. The results show that the thickness of layer and the value of layer have a great effect on the conversion efficiency. Our results suggest a high performance P a-SiC/ I nc-Si/N a-Si structure solar cells with high efficiency of 14.411% and fill factor of 0.738. The simulation result is potentially valuable in exploring gradual bandgap P+a-SiC/I nc-Si/N+a-Si structure solar cells with high performance.

Thin-film Micro-Batteries Based on Metal Nanoparticles

2012 ◽  
Vol 1440 ◽  
Author(s):  
Shuang Peng ◽  
Wenjun Du ◽  
Leela Rakesh ◽  
Axel Mellinger ◽  
Tolga Kaya
Keyword(s):  
Thin Film ◽  
Integrated Circuits ◽  
Metal Nanoparticles ◽  
High Performance ◽  
Low Voltage ◽  
Low Cost ◽  
Open Circuit ◽  
Energy Storage And Conversion ◽  
Battery Capacity ◽  
Zn Nanoparticles

ABSTRACTWe proposed the use of Copper (Cu) and Zinc (Zn) nanoparticles as the electrodes for thin-film microbatteries in the applications of micro-scale sensors. Compared to the widely used lithium-based batteries, Cu and Zn nanoparticles are less expensive, less prone to oxidation (thus involving simpler fabrication steps) and flammability, safe to use, and only requires very simple fabrication processes.Even though the voltage output is inherently smaller (∼1V) than conventional lithium-based batteries, it is sufficient for low-voltage Integrated Circuits (IC) technologies such as 130 nm and 90 nm channel length transistor processes.Commercial paper will be used as the separator to demonstrate the battery capacity. Paper that acts as the separator is slurry-casted with nanoparticles (30-40 nm in size) on both sides. The thickness of the metal nanoparticles-coated thin films and the paper separator are 1 μm and 100 μm, respectively.The electrodes were developed to achieve high conductivity (lower than 1 (Ω·cm)-1) with smooth surface, good adhesion, and flexibility. The metal nanoparticles will be formulated to slurry solutions for screen printing or ink-jet printing for the battery fabrication. For fabrication purposes, the slurries viscosity is approximately in the range of 10-12 cPs at the operating temperature, a surface tension between 28-33 dynes/cm. During the fabrication process including printing/coating and sintering, reductive environment is required to minimize the oxidation. AFM (Atomic Force Microscopy) and EDS (Energy Dispersive Spectroscopy) results will be employed to demonstrate the surface morphology as well as the percentages of metal oxides. Batteries will be tested with and without an ionic liquid for comparison. Humidity effects on the battery performance will also be discussed.Different geometries that are designed to make the batteries with higher voltage or charge will be proposed. Characterization results will include the open-circuit voltage, dielectric property, charging and discharging curve, capacitance and capacity, AFM of the surface test, EDS of the electrodes and the SEM (Scanning Electron microscopy) of the particles.Ourresearch suggest that conductive paper can be scalable and could make high-performance energy storage and conversion devices at low cost and would bring new opportunities for advanced applications.

scholarly journals Influence of Flexibility of the Interconnects on the Dynamic Bending Reliability of Flexible Hybrid Electronics

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 238 ◽  
Author(s):  
Nagarajan Palavesam ◽  
Waltraud Hell ◽  
Andreas Drost ◽  
Christof Landesberger ◽  
Christoph Kutter ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Electronic Systems ◽  
Test Results ◽  
Limited Information ◽  
Silicon Integrated Circuits ◽  
Series Of Experiments ◽  
Dynamic Bending ◽  
Flexible Metal ◽  
Flexible Foils

The growing interest towards thinner and conformable electronic systems has attracted significant attention towards flexible hybrid electronics (FHE). Thin chip-foil packages fabricated by integrating ultra-thin monocrystalline silicon integrated circuits (ICs) on/in flexible foils have the potential to deliver high performance electrical functionalities at very low power requirements while being mechanically flexible. However, only very limited information is available regarding the fatigue or dynamic bending reliability of such chip-foil packages. This paper reports a series of experiments where the influence of the type of metal constituting the interconnects on the foil substrates on their dynamic bending reliability has been analyzed. The test results show that chip-foil packages with interconnects fabricated from a highly flexible metal like gold endure the repeated bending tests better than chip-foil packages with stiffer interconnects fabricated from copper or aluminum. We conclude that further analysis work in this field will lead to new technical concepts and designs for reliable foil based electronics.

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