Design of Standard 12-Lead ECG Acquisition Terminals Based on ADS1298

2013 ◽  
Vol 749 ◽  
pp. 154-159
Author(s):  
Feng Wang ◽  
Hong Yu Jiao ◽  
Ping Zhou
Keyword(s):  
Low Power ◽  
Data Transmission ◽  
High Speed ◽  
Low Noise ◽  
Digital Converter ◽  
Ultra Low Power ◽  
Analog To Digital ◽  
The Core ◽  
Compact Design ◽  
Sd Card

This paper introduced a compact design of portable standard 12-lead ECG acquisition terminals. For portable application purposes, an ultra-low power 16-bit microcontroller, which acted the core unit of the terminal, an 8-channel 24-bit , low-noise low-power high speed,analog-to-digital converter incorporated ECG features,external SD card storage,USB data-transmission module were intergrated into the terminal.Through the terminal,the sampling,storage,transmission and display of standard 12-lead ECG could be implemented in real-time.

scholarly journals A Design of a New Column-Parallel Analog-to-Digital Converter Flash for Monolithic Active Pixel Sensor

2017 ◽  
Vol 2017 ◽  
pp. 1-15 ◽  
Author(s):  
Mostafa Chakir ◽  
Hicham Akhamal ◽  
Hassan Qjidaa
Keyword(s):  
Low Power ◽  
Input Signal ◽  
Small Area ◽  
High Speed ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Active Pixel Sensor ◽  
Analog To Digital ◽  
Active Pixel ◽  
5 Ghz

The CMOS Monolithic Active Pixel Sensor (MAPS) for the International Linear Collider (ILC) vertex detector (VXD) expresses stringent requirements on their analog readout electronics, specifically on the analog-to-digital converter (ADC). This paper concerns designing and optimizing a new architecture of a low power, high speed, and small-area 4-bit column-parallel ADC Flash. Later in this study, we propose to interpose an S/H block in the converter. This integration of S/H block increases the sensitiveness of the converter to the very small amplitude of the input signal from the sensor and provides a sufficient time to the converter to be able to code the input signal. This ADC is developed in 0.18 μm CMOS process with a pixel pitch of 35 μm. The proposed ADC responds to the constraints of power dissipation, size, and speed for the MAPS composed of a matrix of 64 rows and 48 columns where each column ADC covers a small area of 35 × 336.76 μm2. The proposed ADC consumes low power at a 1.8 V supply and 100 MS/s sampling rate with dynamic range of 125 mV. Its DNL and INL are 0.0812/−0.0787 LSB and 0.0811/−0.0787 LSB, respectively. Furthermore, this ADC achieves a high speed more than 5 GHz.

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