Wireless CNC Motion Controller Designed with PSoC

2014 ◽  
Vol 898 ◽  
pp. 944-951 ◽  
Author(s):  
Chi Zhang ◽  
Zhao Hui Ye ◽  
Yong Ming Zhou
Keyword(s):  
High Performance ◽  
System On Chip ◽  
Numerical Control ◽  
Motion Controller ◽  
Joint Axis ◽  
Chip Technology ◽  
On Chip ◽  
Cnc Controller ◽  
The Impact ◽  
Circular Interpolation

Numerical control (NC) technology is a kind of technology combined with electronics, machinery manufacturing, and other interdisciplinary combination of technologies. It is an important part of modern manufacturing. Currently, NC technology is developing towards the open CNC system with extensibility and interchangeability, while the modern electronic technology is developing towards the programmable technology and SoC (System-on-Chip) technology. However, current CNC controller designed with SoC is still in the research stage and not practical yet. In this paper, a practical CNC motion controller is built with modern PSoC (Programmable System-on-Chip) with wireless Ethernet interface. This controller has a high-performance microprocessor, numbers of free configurable analog and digital devices and IO (input/output) interfaces, and many kinds of communication interfaces. Therefore, it has good real-time control functions and communication functions. Experiments for controlling a three joint-axis engraving machine show that the controller can achieve high performance of parallel control of the three joint-axis linear interpolation and two joint-axis circular interpolation, and high performance of the trapezoidal and S-shape speed control. In addition, in order to reduce the impact to the motor and increase the system efficiency, a kind of look-ahead algorithm for velocity control with low time cost is used.

scholarly journals Multiprotocol Authentication Device for HPC and Cloud Environments Based on Elliptic Curve Cryptography

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1148
Author(s):  
Antonio F. Díaz ◽  
Ilia Blokhin ◽  
Mancia Anguita ◽  
Julio Ortega ◽  
Juan J. Escobar
Keyword(s):  
Elliptic Curve ◽  
Elliptic Curve Cryptography ◽  
High Performance ◽  
Low Cost ◽  
System On Chip ◽  
Access To Services ◽  
Multifactor Authentication ◽  
Server Systems ◽  
On Chip ◽  
The Impact

Multifactor authentication is a relevant tool in securing IT infrastructures combining two or more credentials. We can find smartcards and hardware tokens to leverage the authentication process, but they have some limitations. Users connect these devices in the client node to log in or request access to services. Alternatively, if an application wants to use these resources, the code has to be amended with bespoke solutions to provide access. Thanks to advances in system-on-chip devices, we can integrate cryptographically robust, low-cost solutions. In this work, we present an autonomous device that allows multifactor authentication in client–server systems in a transparent way, which facilitates its integration in High-Performance Computing (HPC) and cloud systems, through a generic gateway. The proposed electronic token (eToken), based on the system-on-chip ESP32, provides an extra layer of security based on elliptic curve cryptography. Secure communications between elements use Message Queuing Telemetry Transport (MQTT) to facilitate their interconnection. We have evaluated different types of possible attacks and the impact on communications. The proposed system offers an efficient solution to increase security in access to services and systems.

Multiprocessor transport surveillance video system based on "system on chip" technology

2020 ◽  
Author(s):  
Ш.С. Фахми ◽  
Н.В. Шаталова ◽  
В.В. Вислогузов ◽  
Е.В. Костикова
Keyword(s):  
System On Chip ◽  
Reference Points ◽  
Surveillance Video ◽  
Video Information ◽  
Chip Technology ◽  
Intelligent Video Surveillance System ◽  
Speed Up ◽  
Algorithmic Analysis ◽  
Computational Procedures ◽  
On Chip

В данной работе предлагаются математический аппарат и архитектура многопроцессорной транспортной системы на кристалле (МПТСнК). Выполнена программно-аппаратная реализация интеллектуальной системы видеонаблюдения на базе технологии «система на кристалле» и с использованием аппаратного ускорителя известного метода формирования опорных векторов. Архитектура включает в себя сложно-функциональные блоки анализа видеоинформации на базе параллельных алгоритмов нахождения опорных точек изображений и множества элементарных процессоров для выполнения сложных вычислительных процедур алгоритмов анализа с использованием средств проектирования на базе реконфигурируемой системы на кристалле, позволяющей оценить количество аппаратных ресурсов. Предлагаемая архитектура МПТСнК позволяет ускорить обработку и анализ видеоинформации при решении задач обнаружения и распознавания чрезвычайных ситуаций и подозрительных поведений. In this paper, we propose the mathematical apparatus and architecture of a multiprocessor transport system on a chip (MPTSoC). Software and hardware implementation of an intelligent video surveillance system based on the "system on chip" technology and using a hardware accelerator of the well-known method of forming reference vectors. The architecture includes complex functional blocks for analyzing video information based on parallel algorithms for finding image reference points and a set of elementary processors for performing complex computational procedures for algorithmic analysis. using design tools based on a reconfigurable system on chip that allows you to estimate the amount of hardware resources. The proposed MPTSoC architecture makes it possible to speed up the processing and analysis of video information when solving problems of detecting and recognizing emergencies and suspicious behaviors

scholarly journals Low-Process–Voltage–Temperature-Sensitivity Multi-Stage Timing Monitor for System-on-Chip Applications

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1587
Author(s):  
Duo Sheng ◽  
Hsueh-Ru Lin ◽  
Li Tai
Keyword(s):  
High Performance ◽  
Power Reduction ◽  
System On Chip ◽  
Timing Information ◽  
Multi Stage ◽  
Dynamic Voltage ◽  
And Performance ◽  
On Chip ◽  
Maximum Measurement ◽  
Maximum Measurement Error

High performance and complex system-on-chip (SoC) design require a throughput and stable timing monitor to reduce the impacts of uncertain timing and implement the dynamic voltage and frequency scaling (DVFS) scheme for overall power reduction. This paper presents a multi-stage timing monitor, combining three timing-monitoring stages to achieve a high timing-monitoring resolution and a wide timing-monitoring range simultaneously. Additionally, because the proposed timing monitor has high immunity to the process–voltage–temperature (PVT) variation, it provides a more stable time-monitoring results. The time-monitoring resolution and range of the proposed timing monitor are 47 ps and 2.2 µs, respectively, and the maximum measurement error is 0.06%. Therefore, the proposed multi-stage timing monitor provides not only the timing information of the specified signals to maintain the functionality and performance of the SoC, but also makes the operation of the DVFS scheme more efficient and accurate in SoC design.

A high performance scalable fuzzy based modified Asymmetric Heterogene Multiprocessor System on Chip (AHt-MPSOC) reconfigurable architecture

2021 ◽  
pp. 1-12
Author(s):  
Arun Prasath Raveendran ◽  
Jafar A. Alzubi ◽  
Ramesh Sekaran ◽  
Manikandan Ramachandran
Keyword(s):  
High Performance ◽  
Standard Technique ◽  
System On Chip ◽  
Mixed Integer ◽  
Multiprocessor System ◽  
Compound System ◽  
Available Bandwidth ◽  
Mip Model ◽  
Fpga Chip ◽  
On Chip

This Ensuing generation of FPGA circuit tolerates the combination of lot of hard and soft cores as well as devoted accelerators on a chip. The Heterogene Multi-Processor System-on-Chip (Ht-MPSoC) architecture accomplishes the requirement of modern applications. A compound System on Chip (SoC) system designed for single FPGA chip, and that considered for the performance/power consumption ratio. In the existing method, a FPGA based Mixed Integer Programming (MIP) model used to define the Ht-MPSoC configuration by taking into consideration the sharing hardware accelerator between the cores. However, here, the sharing method differs from one processor to another based on FPGA architecture. Hence, high number of hardware resources on a single FPGA chip with low latency and power targeted. For this reason, a fuzzy based MIP and Graph theory based Traffic Estimator (GTE) are proposed system used to define New asymmetric multiprocessor heterogene framework on microprocessor (AHt-MPSoC) architecture. The bandwidths, energy consumption, wait and transmission range are better accomplished in this suggested technique than the standard technique and it is also implemented with a multi-task framework. The new Fuzzy control-based AHt-MPSoC analysis proves significant improvement of 14.7 percent in available bandwidth and 89.8 percent of energy minimized to various traffic scenarios as compared to conventional method.

scholarly journals Recent Advances in Hearing Aid Technology-A Review

2021 ◽  
Vol 9 (VI) ◽  
pp. 3427-3429
Author(s):  
Animita Das
Keyword(s):  
Hearing Aids ◽  
Hearing Aid ◽  
Cost Effective ◽  
System On Chip ◽  
Audio Signals ◽  
Technology System ◽  
The People ◽  
Chip Technology ◽  
On Chip ◽  
System 1

Hearing aids are electroacoustic gadgets commonly worn in or behind the ear and are intended to enhance the speech Nowadays hearing aids support various application unlike the traditional ones such that it can act like headphones streaming audio signals from internet-enabled devices connected wirelessly via Bluetooth. This paper aims to review the various advancements in the hearing aid technology. System on chip technology of the microcontroller have been used in various studies to develop and design an effective hearing assistant device and help the people with hearing impairment to lead a normal life. Ten articles have been reviewed for the study and it can be concluded that IoT is the future for an efficient, cost effective hearing assistive system [1]

Design of Router Supporting Multiply Routing Algorithm for NoC

2014 ◽  
Vol 981 ◽  
pp. 431-434
Author(s):  
Zhan Peng Jiang ◽  
Rui Xu ◽  
Chang Chun Dong ◽  
Lin Hai Cui
Keyword(s):  
Complex System ◽  
High Performance ◽  
Routing Algorithm ◽  
Network On Chip ◽  
System On Chip ◽  
Low Latency ◽  
Deterministic Routing ◽  
Key Features ◽  
Design Challenge ◽  
On Chip

Network on Chip(NoC)，a new proposed solution to solve global communication problem in complex System on Chip (SoC) design，has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus，and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

scholarly journals A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

2016 ◽  
Vol 11 (01) ◽  
pp. C01059-C01059 ◽  
Author(s):  
R. Bartoldus ◽  
R. Claus ◽  
N. Garelli ◽  
R.T. Herbst ◽  
M. Huffer ◽  
...  
Keyword(s):  
System On Chip ◽  
Readout System ◽  
Chip Technology ◽  
On Chip

Designing of High Performance Multicore Processor with Improved Cache Configuration and Interconnect

2016 ◽  
pp. 204-219
Author(s):  
Ram Prasad Mohanty ◽  
Ashok Kumar Turuk ◽  
Bibhudatta Sahoo
Keyword(s):  
High Performance ◽  
Multicore Processors ◽  
Multicore Processor ◽  
Cache Size ◽  
L2 Cache ◽  
Internal Network ◽  
On Chip ◽  
L1 And L2 ◽  
The Impact ◽  
Cache Configuration

The growing number of cores increases the demand for a powerful memory subsystem which leads to enhancement in the size of caches in multicore processors. Caches are responsible for giving processing elements a faster, higher bandwidth local memory to work with. In this chapter, an attempt has been made to analyze the impact of cache size on performance of Multi-core processors by varying L1 and L2 cache size on the multicore processor with internal network (MPIN) referenced from NIAGRA architecture. As the number of core's increases, traditional on-chip interconnects like bus and crossbar proves to be low in efficiency as well as suffer from poor scalability. In order to overcome the scalability and efficiency issues in these conventional interconnect, ring based design has been proposed. The effect of interconnect on the performance of multicore processors has been analyzed and a novel scalable on-chip interconnection mechanism (INOC) for multicore processors has been proposed. The benchmark results are presented by using a full system simulator. Results show that, using the proposed INoC, compared with the MPIN; the execution time are significantly reduced.

Tofu Interconnect 2: System-on-Chip Integration of High-Performance Interconnect

2014 ◽  
pp. 498-507 ◽  
Author(s):  
Yuichiro Ajima ◽  
Tomohiro Inoue ◽  
Shinya Hiramoto ◽  
Shunji Uno ◽  
Shinji Sumimoto ◽  
...  
Keyword(s):  
High Performance ◽  
System On Chip ◽  
On Chip
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