A High-Resolution Lowpass Sigma-Delta Modulator Applied in Micro-Gyroscope

2014 ◽  
Vol 609-610 ◽  
pp. 964-967
Author(s):  
Jia Jun Zhou ◽  
Di Wang ◽  
Ying Kai Zhao ◽  
Hong Lin Xu ◽  
Xiao Wei Liu
Keyword(s):  
High Resolution ◽  
Dynamic Range ◽  
Sampling Frequency ◽  
Cmos Process ◽  
Effective Number ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
The Stability ◽  
Oversampling Ratio ◽  
Input Level

In this paper, in order to enhance resolution and guarantee the stability of the micro-gyroscope, a high-resolution lowpass sigma-delta modulator is proposed. It employs single-loop fourth-order and full differential structure. The simulated result on the Simulink platform shows that the SNDR is 105.4dB and the effective number of bits (ENOB) is 17.22bits. The entire circuits are implemented with 0.5μm CMOS process. The simulated result on Cadence shows that the SNDR is 99.7dB. The modulator operates at a sampling frequency of 25.6MHz and the signal bandwidth is 100kHz with 128 oversampling ratio (OSR). The dynamic range (DR) is 120 dB approximately and the SNDR changes linearly with the input level.

A High Bandwidth Sigma-Delta Modulator Applied in Micro-Gyroscope

2013 ◽  
Vol 562-565 ◽  
pp. 369-373 ◽  
Author(s):  
Qiang Fu ◽  
Wei Ping Chen ◽  
Song Chen ◽  
Peng Fei Wang ◽  
Xiao Wei Liu
Keyword(s):  
Signal To Noise Ratio ◽  
System Simulation ◽  
Sampling Frequency ◽  
Effective Number ◽  
Signal To Noise ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
High Bandwidth ◽  
Oversampling Ratio ◽  
Input Level

In this paper a fourth-order single-loop sigma-delta modulator applied in micro-gyroscope is designed. The modulator system chose the fully feedforword structure. The signal bandwidth is 200KHz, oversampling ratio is 64 and sampling frequency is 25.6MHz. By system simulation result in Matlab, the signal to noise ratio (SNR) is 92.3dB and effective number of bits (ENOB) is 15.03bits. The whole circuit of modulator is designed and simulated in Cadence Spectre. It is gotten that the SNR is 78.6dB and changes linearly with input level. When input level is bigger than -4dBFs, the modulator becomes overload.

Design of a Fourth-Order Sigma-Delta Modulator for Audio Application

2013 ◽  
Vol 380-384 ◽  
pp. 3580-3583
Author(s):  
Ming Yuan Ren ◽  
Tuo Li ◽  
Chang Chun Dong
Keyword(s):  
High Resolution ◽  
Fourth Order ◽  
High Performance ◽  
Sampling Frequency ◽  
Cmos Process ◽  
Sigma Delta Modulator ◽  
Sigma Delta

Based on requirements on high performance and high resolution of modulators, a fourth-order Sigma-Delta modulator for audio application is developed in this paper. The modulator is designed under the commercial 0.5μm CMOS process and the circuits are given simulations by Spectre. The sampling frequency of sigma-delta modulator is 11.264 MHz, and OSR is 256 within the 22 kHz signal bandwidth. Measure performance shows that Sigma-Delta modulator enables its maximum SNR to achieve 103.5dB, and the accuracy of Sigma-Delta modulator is up to 16 bit.

A 20-MHz BW MASH Sigma–Delta Modulator with Mismatch Noise Randomization for Multi-Bit DACs

2019 ◽  
Vol 29 (07) ◽  
pp. 2050108
Author(s):  
Di Li ◽  
Chunlong Fei ◽  
Qidong Zhang ◽  
Yani Li ◽  
Yintang Yang
Keyword(s):  
Dynamic Range ◽  
Sampling Rate ◽  
Oxide Semiconductor ◽  
Quantization Noise ◽  
Cmos Process ◽  
Noise Shaping ◽  
Signal To Noise ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Chip Area

A high-linearity Multi-stAge noise SHaping (MASH) 2–2–2 sigma–delta modulator (SDM) for 20-MHz signal bandwidth (BW) was presented. Multi-bit quantizers were employed in each stage to provide a sufficiently low quantization noise level and thus improve the signal-to-noise ratio (SNR) performance of the modulator. Mismatch noise in the internal multi-bit digital-to-analog converters (DACs) was analyzed in detail, and an alternative randomization scheme based on multi-layer butterfly-type network was proposed to suppress spurious tones in the output spectrum. Fabricated in a 0.18-[Formula: see text]m single–poly 4-metal Complementary Metal Oxide Semiconductor (CMOS) process, the modulator occupied a chip area of 0.45[Formula: see text]mm2, and dissipated a power of 28.8[Formula: see text]mW from a 1.8-V power supply at a sampling rate of 320[Formula: see text]MHz. The measured spurious-free dynamic range (SFDR) was 94[Formula: see text]dB where 17-dB improvement was achieved by applying the randomizers for multi-bit DACs in the first two stages. The peak signal-to-noise and distortion ratio (SNDR) was 76.9[Formula: see text]dB at [Formula: see text]1 dBFS @ 2.5-MHz input, and the figure-of-merit (FOM) was 126[Formula: see text]pJ/conv.

A Performance Prediction Method with an Equation-Based Behavioral Model for a Single-Bit Single-Loop Sigma-Delta Modulator

2012 ◽  
Vol 4 (4) ◽  
pp. 51-69
Author(s):  
Shuenn-Yuh Lee ◽  
Jia-Hua Hong
Keyword(s):  
Dynamic Range ◽  
Behavioral Model ◽  
Cmos Process ◽  
Switched Capacitor ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Single Loop ◽  
The Real ◽  
Switched Capacitor Circuits ◽  
Real Performance

An equation-based behavioral model has been developed to predict the real performance of a single–loop single-bit Sigma Delta Modulator (SDM). By using this prediction flow, not only can the circuit specifications be acquired, including the gain, bandwidth, slew rate of the OPAMPs, and the capacitor value in the switched-capacitor circuits, but the real performance of the SDM can also be predicted. The switched-capacitor circuits according to the required circuit specifications are employed to design a fourth-order feed-forward (FF) SDM with an over-sampling ratio (OSR) of 64 and a bandwidth of 10kHz using a TSMC 0.35µm CMOS process. The measurement results reveal that the SDM with an input frequency of 2.5kHz and a supply voltage of 3.3V can achieve a dynamic range of 90dB and a spurious-free dynamic range (SFDR) of 85dB under the signal bandwidth of 10kHz and a sampling frequency of 1.28MHz, respectively. The precision of the equation-based behavioral model has been validated by experimental measurements, and its inaccuracy is less than 4%.

Architectural Design and Simulation of a Fourth-Order Sigma-Delta Modulator

2014 ◽  
Vol 609-610 ◽  
pp. 723-727
Author(s):  
Wen Jie Fan ◽  
Qiu Ye Lv ◽  
Chong He ◽  
Liang Yin ◽  
Xiao Wei Liu
Keyword(s):  
Fourth Order ◽  
Architectural Design ◽  
Simple Structure ◽  
Dynamic Range ◽  
Sampling Frequency ◽  
System Level ◽  
Noise Shaping ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Sigma Delta Adc

Sigma-delta ADC outperforms the Nyquist ADC in precision and robustness by using oversampling and noise shaping. A fourth-order sigma-delta modulator of input feedforward architecture is designed and simulated in system-level. Input feedforward architecture has advantages of low output swing of integrators and simple structure. Proper circuit parameters are also presented in this paper. The simulation revealed that the modulator achieves 109 dB dynamic range in a signal bandwidth of 1 KHz with a sampling frequency of 250 KHz.

A 16 Bits Sigma-Delta Modulator Applied in Gyroscope

2014 ◽  
Vol 609-610 ◽  
pp. 1077-1081
Author(s):  
Qiang Fu ◽  
Wei Ping Chen ◽  
Ying Kai Zhao ◽  
Liang Yin ◽  
Xiao Wei Liu
Keyword(s):  
Cmos Process ◽  
Noise Shaping ◽  
Effective Number ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Multi Stage ◽  
Ideal Situation ◽  
Sample Frequency ◽  
Sigma Delta Adc ◽  
The Ideal

In this paper, a 4th-order sigma-delta modulator applied in gyroscope is presented. This modulator adopts the 2-1-1 Multi stage noise shaping structure. The bandwidth of signal is 100 KHz, the over sample rate is 64, and sample frequency is 12.8MHz. By the MATLAB Simulink modeling and simulation, when the input signal is 100 KHz, the SNDR of the MASH ADC is 121.8dB, and the effective number of bit is 19.93 in ideal situation. After considering non-ideal factors, the SNDR is 111.6dB, the effective number of bit of ADC is 18.28. Compared with the ideal situation, the noise floor of PSD has increased 40dB. It explains that non-ideal factors have a significant effect on the performance of the sigma-delta ADC. The 4th-order MASH sigma-delta modulator has been implemented under 0.5 um CMOS process and simulated under Cadence. The final simulation results show that SNDR is 112.4 dB and effective number of bits (ENOB) is 18.6.

A Sigma-Delta Modulator System Design with 1-1-1 Mash Structure

2013 ◽  
Vol 389 ◽  
pp. 568-572
Author(s):  
Ming Xin Song ◽  
Zhi Ming Wang ◽  
Yang Yang
Keyword(s):  
Simulation Model ◽  
System Design ◽  
Input Signal ◽  
Dynamic Range ◽  
Gain Coefficient ◽  
Process Conditions ◽  
Cmos Process ◽  
Audio Frequency ◽  
Sigma Delta Modulator ◽  
Sigma Delta

This paper designs a three cascaded sigma-delta modulator with using mash structure. Analysis of gain coefficient of each module and simulate the modulator for the behavioral level. In 0.5μm CMOS process conditions, the input signal bandwidth is 20 kHz, oversampling rate is 256, SNR of the simulation model can get 100.5 dB, and accuracy is greater than 16 bit. Compared with other structures of the modulator, it has more stable and more dynamic range, so it can be applied to audio-frequency circuit.

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