A Performance Prediction Method with an Equation-Based Behavioral Model for a Single-Bit Single-Loop Sigma-Delta Modulator

2012 ◽  
Vol 4 (4) ◽  
pp. 51-69
Author(s):  
Shuenn-Yuh Lee ◽  
Jia-Hua Hong
Keyword(s):  
Dynamic Range ◽  
Behavioral Model ◽  
Cmos Process ◽  
Switched Capacitor ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Single Loop ◽  
The Real ◽  
Switched Capacitor Circuits ◽  
Real Performance

An equation-based behavioral model has been developed to predict the real performance of a single–loop single-bit Sigma Delta Modulator (SDM). By using this prediction flow, not only can the circuit specifications be acquired, including the gain, bandwidth, slew rate of the OPAMPs, and the capacitor value in the switched-capacitor circuits, but the real performance of the SDM can also be predicted. The switched-capacitor circuits according to the required circuit specifications are employed to design a fourth-order feed-forward (FF) SDM with an over-sampling ratio (OSR) of 64 and a bandwidth of 10kHz using a TSMC 0.35µm CMOS process. The measurement results reveal that the SDM with an input frequency of 2.5kHz and a supply voltage of 3.3V can achieve a dynamic range of 90dB and a spurious-free dynamic range (SFDR) of 85dB under the signal bandwidth of 10kHz and a sampling frequency of 1.28MHz, respectively. The precision of the equation-based behavioral model has been validated by experimental measurements, and its inaccuracy is less than 4%.

A 20-MHz BW MASH Sigma–Delta Modulator with Mismatch Noise Randomization for Multi-Bit DACs

2019 ◽  
Vol 29 (07) ◽  
pp. 2050108
Author(s):  
Di Li ◽  
Chunlong Fei ◽  
Qidong Zhang ◽  
Yani Li ◽  
Yintang Yang
Keyword(s):  
Dynamic Range ◽  
Sampling Rate ◽  
Oxide Semiconductor ◽  
Quantization Noise ◽  
Cmos Process ◽  
Noise Shaping ◽  
Signal To Noise ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Chip Area

A high-linearity Multi-stAge noise SHaping (MASH) 2–2–2 sigma–delta modulator (SDM) for 20-MHz signal bandwidth (BW) was presented. Multi-bit quantizers were employed in each stage to provide a sufficiently low quantization noise level and thus improve the signal-to-noise ratio (SNR) performance of the modulator. Mismatch noise in the internal multi-bit digital-to-analog converters (DACs) was analyzed in detail, and an alternative randomization scheme based on multi-layer butterfly-type network was proposed to suppress spurious tones in the output spectrum. Fabricated in a 0.18-[Formula: see text]m single–poly 4-metal Complementary Metal Oxide Semiconductor (CMOS) process, the modulator occupied a chip area of 0.45[Formula: see text]mm2, and dissipated a power of 28.8[Formula: see text]mW from a 1.8-V power supply at a sampling rate of 320[Formula: see text]MHz. The measured spurious-free dynamic range (SFDR) was 94[Formula: see text]dB where 17-dB improvement was achieved by applying the randomizers for multi-bit DACs in the first two stages. The peak signal-to-noise and distortion ratio (SNDR) was 76.9[Formula: see text]dB at [Formula: see text]1 dBFS @ 2.5-MHz input, and the figure-of-merit (FOM) was 126[Formula: see text]pJ/conv.

The Design of CIFF Structure Three-Order Switched-Capacitor Sigma-Delta Modulator

2012 ◽  
Vol 433-440 ◽  
pp. 5727-5732
Author(s):  
Jun Han ◽  
Wei Dong Wang
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Optimization Technique ◽  
Cmos Technology ◽  
Switched Capacitor ◽  
Clock Frequency ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Transconductance Amplifier ◽  
A Chain

This paper presents the design and implementation of a single-loop three-order switched-capacitor sigma-delta modulator(SDM) with a standard 0.18um CMOS technology. A current optimization technique is utilized in proposed design to reduce the power of operational transconductance amplifier(OTA).Using a chain of Integrators with weighted feed-forward summation(CIFF) structure and optimized single-stage class-A OTA with positive feed-back to minimize the power consumption. The SDM has been presented with an over-sampling ratio of 128,clock frequency 6.144MHz,24kHz band- width, and achieves a peak SNR of 100dB,103dB dynamic range. The whole circuits consume 2.87mW from a single 1.8V supply voltage.

A High-Resolution Lowpass Sigma-Delta Modulator Applied in Micro-Gyroscope

2014 ◽  
Vol 609-610 ◽  
pp. 964-967
Author(s):  
Jia Jun Zhou ◽  
Di Wang ◽  
Ying Kai Zhao ◽  
Hong Lin Xu ◽  
Xiao Wei Liu
Keyword(s):  
High Resolution ◽  
Dynamic Range ◽  
Sampling Frequency ◽  
Cmos Process ◽  
Effective Number ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
The Stability ◽  
Oversampling Ratio ◽  
Input Level

In this paper, in order to enhance resolution and guarantee the stability of the micro-gyroscope, a high-resolution lowpass sigma-delta modulator is proposed. It employs single-loop fourth-order and full differential structure. The simulated result on the Simulink platform shows that the SNDR is 105.4dB and the effective number of bits (ENOB) is 17.22bits. The entire circuits are implemented with 0.5μm CMOS process. The simulated result on Cadence shows that the SNDR is 99.7dB. The modulator operates at a sampling frequency of 25.6MHz and the signal bandwidth is 100kHz with 128 oversampling ratio (OSR). The dynamic range (DR) is 120 dB approximately and the SNDR changes linearly with the input level.

A high-precision interface for tunneling magnetoresistance sensors with 0.15 nT/√Hz resolution

2021 ◽  
Author(s):  
Anqi Chen ◽  
Xiangyu Li ◽  
Yan Li ◽  
Xinpeng Di ◽  
Xiaowei Liu
Keyword(s):  
High Precision ◽  
Integrated Circuit ◽  
Low Noise ◽  
Tunneling Magnetoresistance ◽  
Cmos Process ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Switched Capacitor Circuits ◽  
Fully Differential ◽  
Clock Feedthrough

The tunneling magnetoresistance (TMR) with high-resolution digital output is widely used in military and civil fields. In this work we proposed a low-noise read-out circuit and a four-order fully differential sigma-delta modulator for TMR sensors. In the read-out circuit, we used symmetrical cascade for good matching. We used correlated double sampling (CDS) technique to improve the conversion accuracy of the modulator. In switched capacitor circuits we used time-division multiplexing to suppress charge injection and clock feedthrough. The high-precision application specific integrated circuit (ASIC) chip was fabricated by a 0.35 [Formula: see text]m CMOS process from Shanghai Huahong foundry. The TMR sensor was placed in an environment of three-layer magnetic shielding for test. The active area of the ASIC is only about [Formula: see text]. At a sampling frequency of 20 kHz, the TMR magnetometer consumes 77 mW from a single 5 V supply; the sigma-delta modulator for TMR can achieve an average noise floor of −141 dBV. The magnetometer works at a full scale (FS) of [Formula: see text], it can achieve a nonlinearity of 0.2% FS and a resolution of 0.15 nT/Hz[Formula: see text] over a signal bandwidth.

A Sigma-Delta Modulator System Design with 1-1-1 Mash Structure

2013 ◽  
Vol 389 ◽  
pp. 568-572
Author(s):  
Ming Xin Song ◽  
Zhi Ming Wang ◽  
Yang Yang
Keyword(s):  
Simulation Model ◽  
System Design ◽  
Input Signal ◽  
Dynamic Range ◽  
Gain Coefficient ◽  
Process Conditions ◽  
Cmos Process ◽  
Audio Frequency ◽  
Sigma Delta Modulator ◽  
Sigma Delta

This paper designs a three cascaded sigma-delta modulator with using mash structure. Analysis of gain coefficient of each module and simulate the modulator for the behavioral level. In 0.5μm CMOS process conditions, the input signal bandwidth is 20 kHz, oversampling rate is 256, SNR of the simulation model can get 100.5 dB, and accuracy is greater than 16 bit. Compared with other structures of the modulator, it has more stable and more dynamic range, so it can be applied to audio-frequency circuit.

scholarly journals Second-order sigma-delta modulator in standard cmos technology

2004 ◽  
Vol 1 (3) ◽  
pp. 37-44 ◽  
Author(s):  
Dragisa Milovanovic ◽  
Milan Savic ◽  
Miljan Nikolic
Keyword(s):  
Dynamic Range ◽  
Cmos Technology ◽  
Second Order ◽  
Clock Frequency ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Power Meter ◽  
Sampling Ratio

As a part of wider project sigma-delta modulator was designed. It represents an A/D part of a power meter IC. Requirements imposed were: SNDR and dynamic range > 50 dB for maximum input swing of 250 mV differential at 50 Hz. Over sampling ratio is 128 with clock frequency of 524288 Hz which gives bandwidth of 2048 Hz. Circuit is designed in 3.3 V supply standard CMOS 0.35 ?m technology.

1V supply 16-bit second order Sigma-Delta modulator in a 90nm CMOS process

2012 ◽  
Author(s):  
Rochelle Marie F. Amistoso ◽  
Michael Joe A. Bautista ◽  
Rafael Karlo D.P. Delos Santos ◽  
Joana Rochelle R. Ortiz ◽  
Louis P. Alarcon ◽  
...  
Keyword(s):  
Second Order ◽  
Cmos Process ◽  
Sigma Delta Modulator ◽  
Sigma Delta

Design of Third-Order Single-Loop Full Feed-Forward Sigma Delta Modulator

2014 ◽  
Vol 609-610 ◽  
pp. 1176-1180
Author(s):  
Liang Liu ◽  
Song Chen ◽  
Chong He ◽  
Liang Yin ◽  
Xiao Wei Liu
Keyword(s):  
Model Building ◽  
Inertial Sensors ◽  
Sampling Rate ◽  
Third Order ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Feed Forward ◽  
Single Loop ◽  
Local Feedback ◽  
Sigma Delta Adc

Sigma Delta modulator is widely used in ADC for kinds of micro inertial sensors, Sigma Delta ADC can be easily integrated with digital circuits. It possesses some performances of good linearity and high accuracy, while it has no such strict requirements for the match of device dimensions. In this paper, the design of third-order Sigma Delta modulator with a structure of single-loop full feed-forward is accomplished, meanwhile it uses local feedback for zero optimization to improve the shaping capacity of the modulator noise within the signal bandwidth. The OSR (over-sampling rate) of the modulator is 128 and the signal bandwidth is 10 kHz. By the system model building and simulation in the Simulink of MATALAB, the SNR is 96.3 dB and the ENOB is 15.71 bits. Then the modulator is implemented into transistor-level circuits with 0.5um process, by the simulation in Spectre of Cadence, the SNR is 88.5 dB and the ENOB is 14.41 bits. 搜

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