Surface Treatment of 4H-SiC MOSFETs Prior to Al2O3 Deposition

2020 ◽  
Vol 1004 ◽  
pp. 541-546
Author(s):  
Muhammad Idzdihar Idris ◽  
Alton B. Horsfall
Keyword(s):  
Surface Treatment ◽  
Field Effect ◽  
High Performance ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Surface Treatments ◽  
Flat Band ◽  
Field Effect Mobility ◽  
Mos Capacitors

The effect of surface treatments prior to the deposition of Al2O3 is performed on 4H-SiC MOS capacitors and MOSFETs. 40 nm of Al2O3 were deposited on 4H-SiC using atomic layer deposition (ALD) as a gate dielectric. Different surface treatments were used to investigate the capacitance-voltage and current-voltage characteristics on MOS capacitors and MOSFETs respectively, including the important parameters such as interface state density, flat band voltage, threshold voltage and field-effect mobility. Forming gas annealing and rapid oxidation processes were found to be effective in reducing the interface state density and results in high field-effect mobility with peak field-effect mobility of 130 cm2Vs-1. The experimental results obtained manifest that the surface treatment prior to Al2O3 deposition is critical to producing high performance of 4H-SiC MOSFETs.

Correlation between Field Effect Mobility and Accumulation Conductance at 4H-SiC MOS Interface with Barium

2018 ◽  
Vol 924 ◽  
pp. 477-481
Author(s):  
Kosuke Muraoka ◽  
Seiji Ishikawa ◽  
Hiroshi Sezaki ◽  
Tomonori Maeda ◽  
Shinichiro Kuroki
Keyword(s):  
Linear Correlation ◽  
Field Effect ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Field Effect Mobility ◽  
Mos Capacitors

A correlation between field effect mobility and an accumulation conductance has been investigated at 4H-SiC MOS interface with barium. 4H-SiC n-channel MOSFETs and n-type MOS capacitors were fabricated with a barium-introduced SiO2and a conventional dry SiO2. The field effect mobility was enhanced by introducing the barium-introduced SiO2. It is found that there is a linear correlation between the mobility and the accumulation conductance. The MOS interface of the barium-introduced SiO2had a lower interface state density of 2×1011cm-2eV-1than that of the conventional dry SiO2.

Progress in GaN MOSFET Technology

2008 ◽  
Vol 600-603 ◽  
pp. 1263-1268 ◽  
Author(s):  
T. Paul Chow ◽  
W. Huang ◽  
T. Khan ◽  
K. Matocha ◽  
Y. Wang
Keyword(s):  
Field Effect ◽  
Interface State ◽  
Orientation Dependence ◽  
State Density ◽  
Interface State Density ◽  
Field Effect Mobility ◽  
Mos Capacitors ◽  
Enhancement Mode ◽  
Current Collapse ◽  
Non Destructive

GaN MOS capacitors were characterized to optimize the electric properties of SiO2/GaN interface. With optimized anneal conditions, an interface state density of 3.8×1010/cm2-eV was estimated at 0.19 eV near the conduction band and decreases deeper into the band gap. Enhancement-mode GaN MOSFETs were experimentally demonstrated on both p and n GaN epilayer with record high field-effect mobility of 167 cm2/V-s. Lateral RESURF-type GaN MOSFETs exhibit non-destructive high voltage (up to 940V) blocking capabilities. Other characterization including mobility orientation dependence, MOS-gated Hall mobility, current collapse and an NMOS inverter utilizing E/D mode GaN MOSFETs have also been experimentally demonstrated.

Characterization of Interface State Density from Subthreshold Slope of MOSFETs at Low Temperatures (≥ 10 K)

2015 ◽  
Vol 821-823 ◽  
pp. 745-748
Author(s):  
Hironori Yoshioka ◽  
Junji Senzaki ◽  
Atsushi Shimozato ◽  
Yasunori Tanaka ◽  
Hajime Okumura
Keyword(s):  
Low Temperatures ◽  
Field Effect ◽  
Gate Oxide ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Subthreshold Slope ◽  
Field Effect Mobility ◽  
Peak Field

We have evaluated interface state density (DIT) for EC−ET > 0.00 eV from the subthreshold slope deterioration of MOSFETs at low temperatures. We have compared two n-channel MOSFETs on the C- and a-faces with the gate oxide formed by pyrogenic oxidation followed by annealing in H2. The peak field-effect mobility (µFE,peak) for the C-face MOSFET was 57 cm2V-1s-1 at 300 K, which is lower than the half of 135 cm2V-1s-1 for the a-face MOSFET. We have shown that DIT very close to EC can well explain why µFE for C-face MOSFETs is lower than that for a-face MOSFETs. The value of DIT at 0.00 eV corresponding to the subthreshold slope at 11 K was 1.6×1014 cm-2eV-1 for the C-face MOSFET, which is more than the double of 6.4×1013 cm-2eV-1 for the a-face MOSFET.

Impact of oxide/4H-SiC interface state density on field-effect mobility of counter-doped n-channel 4H-SiC MOSFETs

2021 ◽  
Author(s):  
Takuma Doi ◽  
Shigehisa Shibayama ◽  
Mitsuo Sakashita ◽  
Noriyuki Taoka ◽  
Mitsuaki Shimizu ◽  
...  
Keyword(s):  
Field Effect ◽  
Metal Layer ◽  
Atomic Layer ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Field Effect Mobility ◽  
Free Electron Density ◽  
Layer Deposition ◽  
Rate Of Increase

Abstract We investigated the effect of interface state density on the field-effect mobility (μ FE) of 4H-SiC counter-doped MOSFETs. We fabricated counter-doped MOSFETs with three types of gate oxides i.e., SiO2, Al2O3 formed via atomic layer deposition, and Al2O3 formed via metal layer oxidation (MLO). A maximum μ FE of 80 cm2/Vs was obtained for the MLO-Al2O3 FET, and this value was 60% larger than that of the SiO2 FET. In addition, we evaluated the electron mobility in the neutral channel (μ neutral) and the rate of increase in the free electron density in the neutral channel with respect to the gate voltage (dN neutral/dV G), which are factors determining μ FE. μ neutral depended only on the channel depth, independent of the type of gate oxide. In addition, dN neutral/dV G was significantly low in the SiO2 FET because of carrier trapping at the high density of interface states, whereas this effect was smaller in the Al2O3 FETs.

The Correlation between the Reduction of Interface State Density at the SiO2/SiC Interface and the NO Post-Oxide-Annealing Conditions

2019 ◽  
Vol 954 ◽  
pp. 104-108
Author(s):  
Heng Yu Xu ◽  
Cai Ping Wan ◽  
Jin Ping Ao
Keyword(s):  
Mass Spectrometry ◽  
Secondary Ion Mass Spectrometry ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Mos Capacitors ◽  
Annealing Conditions ◽  
N Concentration ◽  
Higher Temperature ◽  
Secondary Ion

We fabricated SiO2/4H-SiC (0001) MOS capacitors with oxidation temperature at 1350°C, followed by post-oxide-annealing (POA) in NO simply by the control of POA temperatures and times. A correlation between the reduction of interface state density and the increasing of N concentration at the interface has been indicated by C-ψs measurement and secondary ion mass spectrometry (SIMS). The SiO2/4H-SiC interface density decreased when POA temperature was elevated, and the sample annealed at 1300°C for 30min showed the lowest interface state density about 1.5×1012 cm-2eV-1 at Ec-E=0.3 eV when the N concentration is 11.5×1020 cm-3. Meanwhile, the SiO2 /4H-SiC interface annealed at 1200°C for 120min showed the highest N concentration at the 4H-SiC/SiO2 interface is 12.5×1020 cm-3, whereas the interface state density is 2.5×1012 cm-2eV-1 at Ec-E=0.3 eV higher than 1300°C for 30min. The results suggested that higher temperature POA might be much more efficiency in decreased the 4H-SiC MOS interface density with increasing the N area concentration.

Processing and Characterization of MOS Capacitors Fabricated on 2°-Off Axis 4H-SiC Epilayers

2016 ◽  
Vol 858 ◽  
pp. 663-666
Author(s):  
Marilena Vivona ◽  
Patrick Fiorenza ◽  
Tomasz Sledziewski ◽  
Alexandra Gkanatsiou ◽  
Michael Krieger ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Interface State ◽  
State Density ◽  
Metal Oxide Semiconductor ◽  
Interface State Density ◽  
Device Fabrication ◽  
Oxide Semiconductor ◽  
Mos Capacitors ◽  
Oxide Breakdown

In this work, the electrical properties of SiO2/SiC interfaces onto a 2°-off axis 4H-SiC layer were studied and validated through the processing and characterization of metal-oxide-semiconductor (MOS) capacitors. The electrical analyses on the MOS capacitors gave an interface state density in the low 1×1012 eV-1cm-2 range, which results comparable to the standard 4°-off-axis 4H-SiC, currently used for device fabrication. From Fowler-Nordheim analysis and breakdown measurements, a barrier height of 2.9 eV and an oxide breakdown of 10.3 MV/cm were determined. The results demonstrate the maturity of the 2°-off axis material and pave the way for the fabrication of 4H-SiC MOSFET devices on this misorientation angle.

Sign in / Sign up

Export Citation Format

Share Document