Characterization of SiC MOS Structures using Conductance Spectroscopy and Capacitance Voltage Analysis

2000 ◽  
Vol 338-342 ◽  
pp. 1117-1120 ◽  
Author(s):  
Einar Ö. Sveinbjörnsson ◽  
M. Ahnoff ◽  
H.Ö. Ólafsson
Keyword(s):  
Capacitance Voltage ◽  
Mos Structures

Electrical Characterization of Al2O3 - SiO2 Mos Structures

1999 ◽  
Vol 567 ◽  
Author(s):  
L-Å Ragnarsson ◽  
E. Aderstedt ◽  
P. Lundgren
Keyword(s):  
Electrical Characterization ◽  
Thickness Reduction ◽  
Initial Thickness ◽  
Equivalent Thickness ◽  
Conventional Furnace ◽  
Capacitance Voltage ◽  
Layered Dielectric ◽  
The Impact ◽  
Mos Structures

ABSTRACTA comparative capacitance voltage method is used to investigate the equivalent thickness reduction during post metallization annealing of thermally grown ultrathin (∼15-27 Å) oxides. It is found that a double layered dielectric consisting of a thin Al2O3—SiO2 sandwich is appropriate to describe both the increased capacitance and the nearly unaltered current after anneal. It is further shown that the impact of initial thickness and method of growth — in a conventional furnace or by rapid thermal oxidation — on the equivalent thickness reduction is negligible.

Atomic Layer Deposition of Al2O3 Thin Films for Metal Insulator Semiconductor Applications on 4H-SiC

2016 ◽  
Vol 858 ◽  
pp. 685-688 ◽  
Author(s):  
Emanuela Schilirò ◽  
Salvatore di Franco ◽  
Patrick Fiorenza ◽  
Corrado Bongiorno ◽  
Hassan Gargouri ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Atomic Layer Deposition ◽  
Atomic Layer ◽  
Gate Insulator ◽  
Metal Insulator ◽  
Layer Deposition ◽  
Capacitance Voltage ◽  
Mos Structures ◽  
Thermally Grown

This work reports on the growth and characterization of Al2O3 films on 4H-SiC, by Plasma Enhanced-Atomic Layer Deposition (PE-ALD). Different techniques were used to investigate the morphological, structural and electrical features of the Al2O3 films, both with and without the presence of a thin SiO2 layer, thermally grown on the 4H-SiC before ALD. Capacitance-voltage measurements on MOS structures resulted in a higher dielectric constant (ε~8.4) for the Al2O3/SiO2/SiC stack, with respect to that of the Al2O3/SiC sample (ε~ 6.7). Moreover, C<em>urrent density-Electric Field</em> measurements demonstrated a reduction of the leakage current and an improvement of the breakdown behaviour in the presence of the interfacial thermally grown SiO2. Basing on these preliminary results, possible applications of ALD-Al2O3 as gate insulator in 4H-SiC MOSFETs can be envisaged.

Characterization of the SiO2/SiC Interface with Impedance Spectroscopy

2009 ◽  
Vol 615-617 ◽  
pp. 501-504 ◽  
Author(s):  
Pawel A. Sobas ◽  
Ulrike Grossner ◽  
Bengt Gunnar Svensson
Keyword(s):  
Impedance Spectroscopy ◽  
Ionic Conduction ◽  
Semiconductor Interface ◽  
Transfer Processes ◽  
Capacitance Voltage ◽  
Dc Bias ◽  
The One ◽  
Cv Measurements ◽  
Mos Structures

Using impedance spectroscopy (IS) for the characterization of SiO2/4H-SiC (MOS) structures, insight on the capacitive and resistive contributions in different physical regions of the MOS structures is obtained. Changing the DC bias conditions, semiconductor, interface as well as oxide traps can be detected. The MOS capacitance, as extracted from IS data, is different from the one obtained using capacitance voltage (CV) measurements, due to the possibility of distinguishing different charge transfer processes using IS. For instance, in the investigated capacitors, a clear contribution is revealed from ionic conduction processes at bias voltages close to zero.

Nanoprobe Characterization of Soft SRAM bit Fails in Advanced Technologies

2019 ◽  
Author(s):  
Satish Kodali ◽  
Chen Zhe ◽  
Chong Khiam Oh
Keyword(s):  
Yield Loss ◽  
Performance Metrics ◽  
Root Cause ◽  
Advanced Technologies ◽  
Capacitance Voltage ◽  
Defect Localization ◽  
Cv Measurements ◽  
Lightly Doped Drain ◽  
Dc Characterization

Abstract Nanoprobing is one of the key characterization techniques for soft defect localization in SRAM. DC transistor performance metrics could be used to identify the root cause of the fail mode. One such case report where nanoprobing was applied to a wafer impacted by significant SRAM yield loss is presented in this paper where standard FIB cross-section on hard fail sites and top down delayered inspection did not reveal any obvious defects. The authors performed nanoprobing DC characterization measurements followed by capacitance-voltage (CV) measurements. Two probe CV measurement was then performed between the gate and drain of the device with source and bulk floating. The authors identified valuable process marginality at the gate to lightly doped drain overlap region. Physical characterization on an inline split wafer identified residual deposits on the BL contacts potentially blocking the implant. Enhanced cleans for resist removal was implemented as a fix for the fail mode.

dC/dV and CV Characterization of Gate Resistance Defects in eDRAM Circuits

2013 ◽  
Author(s):  
Sweta Pendyala ◽  
Dave Albert ◽  
Katherine Hawkins ◽  
Michael Tenney
Keyword(s):  
Deep Submicron ◽  
Work Flow ◽  
Localization Technique ◽  
Characterization Techniques ◽  
Capacitance Voltage ◽  
Gate Resistance

Abstract Resistive gate defects are unusual and difficult to detect with conventional techniques [1] especially on advanced devices manufactured with deep submicron SOI technologies. An advanced localization technique such as Scanning Capacitance Imaging is essential for localizing these defects, which can be followed by DC probing, dC/dV, CV (Capacitance-Voltage) measurements to completely characterize the defect. This paper presents a case study demonstrating this work flow of characterization techniques.

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