The Preparation of World-Class Single Crystal Silicon Carbide Wafers Using High Rate Chemical Mechanical Planarization Slurries

2008 ◽  
Vol 600-603 ◽  
pp. 839-842 ◽  
Author(s):  
Michael L. White ◽  
Stan Reggie ◽  
Nevin Naguib ◽  
Kenneth Nicholson ◽  
Jeffrey Gilliland ◽  
...  
Keyword(s):  
Activation Energy ◽  
Silicon Carbide ◽  
Kinetic Analysis ◽  
Removal Rate ◽  
Chemical Mechanical Planarization ◽  
Single Crystal Silicon ◽  
High Rate ◽  
Crystal Silicon ◽  
World Class ◽  
Planarization Process

The influence of the chemical mechanical planarization process on the 4o off-axis 4HN SiC removal rate for silicon carbide slurry produced by Cabot Microelectronics Corporation (CMC) has been studied. A detailed kinetic analysis was applied and the linearity of an Arrhenius-like activation energy plot suggests that the primary removal occurs from particles adhered to the pad surface.

scholarly journals Novel Abrasive-Impregnated Pads and Diamond Plates for the Grinding and Lapping of Single-Crystal Silicon Carbide Wafers

2021 ◽  
Vol 11 (4) ◽  
pp. 1783
Author(s):  
Ming-Yi Tsai ◽  
Kun-Ying Li ◽  
Sun-Yu Ji
Keyword(s):  
Silicon Carbide ◽  
Wear Rate ◽  
Single Crystal ◽  
Traditional Method ◽  
Removal Rate ◽  
Chemical Mechanical Planarization ◽  
Single Crystal Silicon ◽  
Crystal Silicon ◽  
Diamond Grit ◽  
Ceramic Binder

In this study, special ceramic grinding plates impregnated with diamond grit and other abrasives, as well as self-made lapping plates, were used to prepare the surface of single-crystal silicon carbide (SiC) wafers. This novel approach enhanced the process and reduced the final chemical mechanical planarization (CMP) polishing time. Two different grinding plates with pads impregnated with mixed abrasives were prepared: one with self-modified diamond + SiC and a ceramic binder and one with self-modified diamond + SiO2 + Al2O3 + SiC and a ceramic binder. The surface properties and removal rate of the SiC substrate were investigated and a comparison with the traditional method was conducted. The experimental results showed that the material removal rate (MRR) was higher for the SiC substrate with the mixed abrasive lapping plate than for the traditional method. The grinding wear rate could be reduced by 31.6%. The surface roughness of the samples polished using the diamond-impregnated lapping plate was markedly better than that of the samples polished using the copper plate. However, while the surface finish was better and the grinding efficiency was high, the wear rate of the mixed abrasive-impregnated polishing plates was high. This was a clear indication that this novel method was effective and could be used for SiC grinding and lapping.

High Rate Silicon Carbide Polishing to Ultra-smooth Surfaces

2007 ◽  
Vol 991 ◽  
Author(s):  
Michael White ◽  
Kevin Moeggenborg ◽  
Francois Batllo ◽  
Jeffrey Gilliland ◽  
Nevin Naguib
Keyword(s):  
Silicon Carbide ◽  
Integrated Circuit ◽  
Chemical Mechanical Planarization ◽  
Streaming Potential ◽  
Single Crystal Silicon ◽  
High Hardness ◽  
High Rate ◽  
Removal Rates ◽  
Crystal Silicon ◽  
Light Emitting

ABSTRACTSilicon Carbide has a unique combination of properties that include a nearly diamond-like hardness, intrinsic electrical semiconductivity and a high thermal conductivity. This combination of properties has led to it's use in a number of applications including substrates for Light Emitting Diodes (LEDs), power, RF (radio frequency) and other electronic devices in addition to mirror substrates and optical devices as well as stop layers in integrated circuit chip manufacture. In addition, the chemical inertness and high hardness of SiC has historically resulted in low removal rates during chemical mechanical Planarization (CMP). Recent efforts in our labs have led to being able to polish single crystal silicon carbide at removal rates up to 400 nm/hr yielding a root mean squared roughness on the order of a nanometer as determined by AFM and interferometry. The high rates and smoothness obtained are expected to translate to other types of silicon carbide. Fundamental studies by FTIR, streaming potential and ESCA have been done to elucidate the mechanism of silicon carbide polishing.

Silicon Carbide Die Attach Scheme for 500°C Operation

2000 ◽  
Vol 622 ◽  
Author(s):  
Liang-Yu Chen ◽  
Gary W. Hunter ◽  
Philip G. Neudeck
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Electrical Resistance ◽  
Room Temperature ◽  
Semiconductor Devices ◽  
Single Crystal Silicon ◽  
Film Material ◽  
Crystal Silicon ◽  
Pure Alumina ◽  
Die Attach

ABSTRACTSingle crystal silicon carbide (SiC) has such excellent physical, chemical, and electronic properties that SiC based semiconductor electronics can operate at temperatures in excess of 600°C well beyond the high temperature limit for Si based semiconductor devices. SiC semiconductor devices have been demonstrated to be operable at temperatures as high as 600°C, but only in a probe-station environment partially because suitable packaging technology for high temperature (500°C and beyond) devices is still in development. One of the core technologies necessary for high temperature electronic packaging is semiconductor die-attach with low and stable electrical resistance. This paper discusses a low resistance die-attach method and the results of testing carried out at both room temperature and 500°C in air. A 1 mm2 SiC Schottky diode die was attached to aluminum nitride (AlN) and 96% pure alumina ceramic substrates using precious metal based thick-film material. The attached test die using this scheme survived both electronically and mechanically performance and stability tests at 500°C in oxidizing environment of air for 550 hours. The upper limit of electrical resistance of the die-attach interface estimated by forward I-V curves of an attached diode before and during heat treatment indicated stable and low attach-resistance at both room-temperature and 500°C over the entire 550 hours test period. The future durability tests are also discussed.

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