Silicon Carbide Die Attach Scheme for 500°C Operation

2000 ◽  
Vol 622 ◽  
Author(s):  
Liang-Yu Chen ◽  
Gary W. Hunter ◽  
Philip G. Neudeck
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Electrical Resistance ◽  
Room Temperature ◽  
Semiconductor Devices ◽  
Single Crystal Silicon ◽  
Film Material ◽  
Crystal Silicon ◽  
Pure Alumina ◽  
Die Attach

ABSTRACTSingle crystal silicon carbide (SiC) has such excellent physical, chemical, and electronic properties that SiC based semiconductor electronics can operate at temperatures in excess of 600°C well beyond the high temperature limit for Si based semiconductor devices. SiC semiconductor devices have been demonstrated to be operable at temperatures as high as 600°C, but only in a probe-station environment partially because suitable packaging technology for high temperature (500°C and beyond) devices is still in development. One of the core technologies necessary for high temperature electronic packaging is semiconductor die-attach with low and stable electrical resistance. This paper discusses a low resistance die-attach method and the results of testing carried out at both room temperature and 500°C in air. A 1 mm2 SiC Schottky diode die was attached to aluminum nitride (AlN) and 96% pure alumina ceramic substrates using precious metal based thick-film material. The attached test die using this scheme survived both electronically and mechanically performance and stability tests at 500°C in oxidizing environment of air for 550 hours. The upper limit of electrical resistance of the die-attach interface estimated by forward I-V curves of an attached diode before and during heat treatment indicated stable and low attach-resistance at both room-temperature and 500°C over the entire 550 hours test period. The future durability tests are also discussed.

Silicon Carbide: Progress in Crystal Growth

1987 ◽  
Vol 97 ◽  
Author(s):  
J. Anthony Powell
Keyword(s):  
Silicon Carbide ◽  
Crystal Growth ◽  
High Temperature ◽  
Epitaxial Growth ◽  
Recent Progress ◽  
Single Crystal Silicon ◽  
Silicon Substrates ◽  
Large Area ◽  
High Quality ◽  
Crystal Silicon

ABSTRACTSilicon carbide (SiC), with a favorable combination of semiconducting and refractory properties, has long been a candidate for high temperature semiconductor applications. Research on processes for producing the needed large-area high quality single crystals has proceeded sporadically for many years. Two characteristics of SiC have aggravated the problem of its crystal growth. First, it cannot be melted at any reasonable pressure, and second, it forms many different crystalline structures, called polytypes. Recent progress in the development of two crystal growth processes will be described. These processes are the modified Lely process for the growth of the alpha polytypes (e.g. 6H SiC), and a process for the epitaxial growth of the beta polytype (i.e. 3C or cubic SiC) on single crystal silicon substrates. A discussion of the semiconducting qualities of crystals grown by various techniques will also be included.

Thermal Conductivity of Porous Silicon Layers for MEMS

1999 ◽  
Author(s):  
Uma Srinivasan ◽  
Peter Breh ◽  
Mehdi Asheghi ◽  
Maxat Touzelbaev ◽  
Kenneth E. Goodson
Keyword(s):  
Thermal Conductivity ◽  
Porous Silicon ◽  
Electrical Resistance ◽  
Room Temperature ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Boundary Scattering ◽  
Conductivity Data ◽  
Crystal Silicon ◽  
Resistance Thermometry

Abstract Porous silicon is a promising material for MEMS because of its unique electrical, thermal, optical, and absorptive properties. This work measures the thermal conductivity of a silicon layer with 40 percent porosity at temperatures between 20 and 300 K using Joule heating and electrical-resistance thermometry. The room-temperature thermal conductivity is 0.43 Wm−1K−1, which is almost three orders of magnitude less than the value for single-crystal silicon. The data are interpreted using a new model based on electron microscopy, which shows a sponge-like morphology with embedded crystalline regions. The model separately treats the contributions of the sponge-like material, in which the solid regions are assumed to be amorphous silicon, and the larger crystallites, in which the conductivity is reduced by boundary scattering. The present work is particularly useful for MEMS based on silicon with porosity below 50 percent, for which no thermal conductivity data were previously available.

HREM observation of dislocations near room temperature fractures in silicon

1988 ◽  
Vol 46 ◽  
pp. 892-893
Author(s):  
M. H. Rhee ◽  
W. A. Coghlan
Keyword(s):  
Cross Section ◽  
Room Temperature ◽  
Single Crystal Silicon ◽  
Dislocation Nucleation ◽  
Back Side ◽  
Ion Milling ◽  
Crystal Silicon ◽  
Flat Surfaces ◽  
Induced Fractures ◽  
Vicker’S Microhardness

Silicon is believed to be an almost perfectly brittle material with cleavage occurring on {111} planes. In such a material at room temperature cleavage is expected to occur prior to any dislocation nucleation. This behavior suggests that cleavage fracture may be used to produce usable flat surfaces. Attempts to show this have failed. Such fractures produced in semiconductor silicon tend to occur on planes of variable orientation resulting in surfaces with a poor surface finish. In order to learn more about the mechanisms involved in fracture of silicon we began a HREM study of hardness indent induced fractures in thin samples of oxidized silicon.Samples of single crystal silicon were oxidized in air for 100 hours at 1000°C. Two pieces of this material were glued together and 500 μm thick cross-section samples were cut from the combined piece. The cross-section samples were indented using a Vicker's microhardness tester to produce cracks. The cracks in the samples were preserved by thinning from the back side using a combination of mechanical grinding and ion milling.

scholarly journals Novel Abrasive-Impregnated Pads and Diamond Plates for the Grinding and Lapping of Single-Crystal Silicon Carbide Wafers

2021 ◽  
Vol 11 (4) ◽  
pp. 1783
Author(s):  
Ming-Yi Tsai ◽  
Kun-Ying Li ◽  
Sun-Yu Ji
Keyword(s):  
Silicon Carbide ◽  
Wear Rate ◽  
Single Crystal ◽  
Traditional Method ◽  
Removal Rate ◽  
Chemical Mechanical Planarization ◽  
Single Crystal Silicon ◽  
Crystal Silicon ◽  
Diamond Grit ◽  
Ceramic Binder

In this study, special ceramic grinding plates impregnated with diamond grit and other abrasives, as well as self-made lapping plates, were used to prepare the surface of single-crystal silicon carbide (SiC) wafers. This novel approach enhanced the process and reduced the final chemical mechanical planarization (CMP) polishing time. Two different grinding plates with pads impregnated with mixed abrasives were prepared: one with self-modified diamond + SiC and a ceramic binder and one with self-modified diamond + SiO2 + Al2O3 + SiC and a ceramic binder. The surface properties and removal rate of the SiC substrate were investigated and a comparison with the traditional method was conducted. The experimental results showed that the material removal rate (MRR) was higher for the SiC substrate with the mixed abrasive lapping plate than for the traditional method. The grinding wear rate could be reduced by 31.6%. The surface roughness of the samples polished using the diamond-impregnated lapping plate was markedly better than that of the samples polished using the copper plate. However, while the surface finish was better and the grinding efficiency was high, the wear rate of the mixed abrasive-impregnated polishing plates was high. This was a clear indication that this novel method was effective and could be used for SiC grinding and lapping.

Oxidation of Single‐Crystal Silicon Carbide: Part I . Experimental Studies

1990 ◽  
Vol 137 (3) ◽  
pp. 854-858 ◽  
Author(s):  
Z. Zheng ◽  
R. E. Tressler ◽  
K. E. Spear
Keyword(s):  
Silicon Carbide ◽  
Single Crystal ◽  
Experimental Studies ◽  
Single Crystal Silicon ◽  
Crystal Silicon

Electronic Properties of Femtosecond Laser Induced Modified Spots on Single Crystal Silicon Carbide

2010 ◽  
Vol 645-648 ◽  
pp. 239-242 ◽  
Author(s):  
Takuro Tomita ◽  
M. Iwami ◽  
M. Yamamoto ◽  
M. Deki ◽  
Shigeki Matsuo ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Femtosecond Laser ◽  
Single Crystal ◽  
Specific Resistance ◽  
Single Crystal Silicon ◽  
Metal Contacts ◽  
Crystal Silicon ◽  
Current Voltage ◽  
Fs Laser ◽  
Current Voltage Characteristics

Femtosecond (fs) laser modification on single crystal silicon carbide (SiC) was studied from the viewpoints of electric conductivity. Fourier transform infrared (FTIR) spectroscopy was carried out on femtosecond laser modified area. The intensity decrease of reststrahlen band due to the modification was observed, and this decrease was explained by the degradation of crystallinity due to the laser irradiation. Polarization dependence of reststrahlen band was also observed on laser modified samples. Current-voltage characteristics and Hall measurements on fs-laser modified region were carried out by fabricating the metal contacts on the ion implanted areas. The specific resistance up to 5.9×10-2 m was obtained for fs-laser modified area.

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